SemiWiki

Is Your Synchronizer Doing its Job (Part 1)?

Tue, 18 Jun 2013 18:30:00 -0700

Recently, I discussed the increasing risk of metastability hazards at nanoscale geometries. These risks are significantly aggravated at low supply voltages and low temperatures and must be addressed during the design cycle of any mission critical application. This time I discuss what it takes to estimate a synchronizer�s mean-time between failures (MTBF).

Some flip-flops do a better job as a synchronizer than others. Sometimes you need to cascade flip-flops to get the MTBF your customer�s product needs. As the project manager, how are you going to decide about these issues when the engineer that

Derivative Designs Need Tools Too

Tue, 18 Jun 2013 09:58:00 -0700

Increasingly, SoC designs consist of assembling blocks of pre-designed IP. One special case is the derivative design where not just the IP blocks get re-used but a lot of the assembly itself. For example, in the design below some blocks are added, some blocks are updated,

Increasing Automotive Semiconductor Test Quality

Mon, 17 Jun 2013 14:45:00 -0700

The growing amount of electronics within today�s automobiles is driving very high quality and reliability requirements to a widening

Formality Ultra, Streamline Your ECOs

Mon, 17 Jun 2013 06:00:00 -0700

One of the most challenging stages in an SoC design is achieving timing closure. Actually design closure is perhaps a better term since everything needs to come together such as clock tree, power nets, power budget and so on. Changes made to the design are known as ECOs (which stands for engineering change orders, a term that comes from the days when circuit boards would have colored wires added to address problems, try that on a 20nm chip). Some ECOs are minor timing changes but some are more significant and require RTL changes. This stage of the design cycle can take weeks, with multiple ECO cycles each of which requires many engineers for a few week.

The challenge with ECOs is two fold. First is to avoid the whack-a-mole problem whereby each change fixes

Taiwan Semiconductor Tries To Pull A FinFAST One!

Sun, 16 Jun 2013 19:00:00 -0700

This completely misleading title is from a Seeking Alpha (SA) article, a stock investment version of the National Enquirer. As I mentioned in A

Should You Buy All Aspects of Your IP From a Single Supplier?

Sun, 16 Jun 2013 07:18:00 -0700
Interface IP typically consists of multiple layers, most importantly a PHY (level 1) analog (or mixed signal) block that handles the interface to the outside world and a number of levels of digital controllers. The interfaces between all these levels, especially between the PHY and the controller, is often defined by the interface standard. So, in principle, any PHY should work with any controller. Verification IP should work with any block. And so on.

Virtual platforms enable software development to take place on a model of an electronic system. What everyone would like is models that are fast and accurate but that is simply not possible. Fast models are fast because they don�t model everything at the signal level.

Eldo and Pyxis from Mentor, DAC Update

Thu, 13 Jun 2013 11:15:00 -0700
Last Monday at DAC I met with Linda Fosler, Marketing Director at Mentor Graphics to get an update on what's new with Eldo (Circuit simulator) and Pyxis (custom IC layout and schematic).

Calibre Update at DAC

Thu, 13 Jun 2013 10:51:00 -0700
Mentor Graphics throws a very nice dinner party at DAC each year for journalists, bloggers and top customers, so this year I spoke with Michael Buehler-Garcia about what's new with Calibre.

Tela Innovations filed a huge complaint back in February with the U.S. International Trade Commission (USITC) against HTC Corporation; HTC America, Inc.; LG Electronics, Inc.; LG Electronics U.S.A., Inc.; LG Electronics MobileComm U.S.A., Inc.; Motorola Mobility LLC; Nokia Corporation; Nokia, Inc.; Pantech Co., Ltd.; and Pantech Wireless, Inc.

At DAC last week I met with Neal Carney to get an update on what Tela Innovations is up to this year.