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    Thanks to Arteris for evangelization blog dealing with High Speed Interfaces! 

    by
    Eric Esteve
    Published on 04-15-2012 02:36 AM
    content/attachments/3398-2%24-savings-c2c.jpg.html

    Kurt Shuler from Arteris has written a short but useful blog about the various high speed interface protocols currently used in the wireless handset (and smartphone) IP ecosystem. Arteris is well known for their flagship product, the Network-on-Chip (NoC), and the Mobile Application Processor market segment represent the first target for NoC: NoC is the IP which help increasing overall chip performance by optimizing internal interconnect, allows ...
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    Virtual Prototype your SoC including FlexNoC and optimize your SoC architecture decision before 

    by
    Eric Esteve
    Published on 03-12-2012 11:10 AM
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    Designing larger than ever SoC, integrating multiple ARM’s Cortex-A15 and Cortex-A9 microprocessor cores as well as complexes IP functions like HDMI controller, DDR3 Memory controller, Ethernet, SATA or PCI Express controller are pushing designers to search for better price, performance and area tradeoffs and the SoC interconnect plays a vital role in serving this need. Using an ...
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    Synopsys MIPI M-PHY in 28nm introduction, supporting CSI-3, DSI-2, UFS, DigRF v4, SSIC and LLI (with Arteris) 

    by
    Eric Esteve
    Published on 02-29-2012 06:05 AM
    content/attachments/3014-m-phy-6-protocols.jpg.html

    MIPI set of specifications (supported by dedicated controllers) are completed by a PHY function, the D-PHY or the M-PHY function. The D-PHY was the first to be released, and most of the MIPI functions supported in a smartphone we are using today probably still use a D-PHY, but the latest MIPI specifications have been developed based on the M-PHY usage. Which does not means that the D-PHY will disappear any soon, but clearly M-PHY is the future…

    At the early ...
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    Multicore SoC Architecture Optimization: when Arteris and Synopsys team together 

    by
    Eric Esteve
    Published on 02-16-2012 03:36 AM
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    Once again with Synopsys and Arteris, the innovation is coming to solve an issue, faced by their potential customers: "In our research, we've found that almost half of project delays are caused by problems with the system architecture design and specification," said Chris Rommel, vice president, embedded software and hardware, VDC Research. "Many of these architecture problems are related to escalating SoC complexity, including multicore requirements. Therefore, solutions ...
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    Arteris vs Sonics battle: remind Clausewitz! 

    by
    Eric Esteve
    Published on 01-29-2012 11:56 AM
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    I have blogged before Christmas about the Arteris-Sonics war, initiated by Sonics, claiming that Arteris NoC IP product was infringing Sonics patent. We had shown in this post that the architecture of Sonics interconnects IP product was not only older but also different from Arteris’ NoC architecture: the products launched initially by Sonics, in the 1995-2000 years, were closer to a crossbar switch than to a Network-on-Chip. Having ...
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    NoC for faster SoC integration 

    by
    Eric Esteve
    Published on 01-19-2012 03:32 AM
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    The need for Network-on-Chip (NoC) has appeared at the time where chip makers realized that they could really integrate a complete system on a single die to build a System-on-Chip (SoC). I was in charge of the development of a large IC, integrating different type of functions (Analog and Digital) to support advanced TV application. It was a long development, far to be easy, but the chip was ...
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    Arteris White Papers: how to use NoC to avoid routing congestion 

    by
    Eric Esteve
    Published on 11-23-2011 03:21 AM
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    Network-on-Chip (NoC) is an emerging paradigm for communications within large VLSI systems implemented on a single silicon chip. Sgroi et al. call "the layered-stack approach to the design of the on-chip intercore communications the Network-on-Chip (NOC) methodology." In a NoC system, modules such as processor cores, memories and specialized IP ...
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