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    by Published on 12-14-2014 06:00 PM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/12758-flexnoc-resilience-package-block-diagram-copy.jpg

    System-on-chip (SoC) devices are increasingly becoming more complex in terms of adding functionality yet they need to be more reliable and fault tolerant for automotive, aerospace and industrial electronics.

    Arteris Inc.—which invented the network-on-chip (NoC) interconnect technology ...
    by Published on 11-19-2014 02:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/12589-arteris-collage.jpg

    When Arteris sold key network-on-chip intellectual property and most of its human assets to Qualcomm earlier this year, it was big news. We suggested the bigger news after a restaffing effort would be a next-generation NoC release, and a new round of design wins.

    Some developments were already in the pipeline. ...
    by Published on 10-13-2014 03:00 PM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/12224-flexnoc-resilience-package.jpg

    Protecting memory with ECC but leaving the rest of an SoC uncovered is like having a guard dog chained up in the back corner of your yard. If the problem happens to be in that particular spot, it’ll be dealt with, otherwise there will be a lot of barking but little actual protection.

    Similarly, adding a safety-capable processor like an ARM Cortex-R or a Synopsys DesignWare EM SEP core in a dual-core lockstep configuration is only part of the answer for protecting SoCs.
    ...
    by Published on 09-14-2014 03:00 PM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/12030-trw-semi-automated-driving.jpg

    Flip on the TV, and a car commercial is bound to pop up shortly touting one of two technological aspects. One is center stack integration of smartphone-style applications. The other is advanced driver assistance systems (ADAS) featuring cameras, radar, and other sensors helping cars ...
    by Published on 08-28-2014 03:00 PM
    1. Categories:
    2. Semiconductor IP,
    3. FPGA,
    4. Arteris
    content/attachments/11912-altera-arria-10-mpsoc-system-interconnect.jpg

    Advantages to using NoCs in SoC design are well documented: reduced routing congestion, better performance than crossbars, improved optimization and reuse of IP, strategies for system power management, and so on. What happens when NoCs move into FPGAs, or more accurately the SoC variant combining ARM cores ...
    by Published on 07-23-2014 06:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/11626-dvfs-concept.jpg

    Most of the buzz on network-on-chip is around simplifying and scaling interconnect, especially in multicore SoCs where AMBA buses and crossbars run into issues as more and more cores enter a design. Designers may want to explore how NoCs can help with a more power-aware approach. ...
    by Published on 07-01-2014 09:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/11462-marvell-logo.jpg

    If you hang around engineers for any time at all, the word optimization is bound to come up. The very definition of engineer is to contrive or devise a solution. With that anointing, most engineers are beholden to the idea that their job is creating, synthesizing, and perfecting a solution specifically for the needs of a unique situation. ...
    Published on 05-08-2014 10:30 PM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/10976-2014-05-07_conclusion.jpg

    The Linley Mobile Conference last week initiated a lot of discussion about emerging technologies and markets, especially wearables. Jessica Lipsky’s EE Times article captured some of the sentiments in her article, “Wearables Need Tailored SoCs.” But the conference covered a lot more ground than wearables, including mobile security, benchmarking, heterogeneous multicore computing, and always-on coprocessing.

    You can download my “SoC Design Challenges of Wearables” presentation here: ...
    Published on 04-30-2014 08:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/10877-2014-04-23_marine.jpg

    The Electronic Design Process Symposium is an annual workshop run by the IEEE Computer Society of Silicon Valley and the IEEE Council on Electronic Design Automation. I presented there because it’s devoid of product marketing pitches, and is two days of discussion on technical and process issues in SoC design. My slides are here:

    http://www.eda.org/edps/Papers/4-3%20Kurt%20Shuler.pdf

    My task for the presentation was to explain how IP reuse and the explosion in on-chip functionality has changed ...
    by Published on 04-17-2014 05:30 PM
    1. Categories:
    2. Semiconductor IP,
    3. Arteris
    content/attachments/10769-cisco-common-ioe-platform-architecture.jpg

    In his recent blog on EETimes, Kurt Shuler of Arteris took a whimsical look at the hype surrounding the IoT, questioning the overall absence of practicality and a seemingly misplaced focus on use cases at the expense of a coherent architecture. I don’t think it is all that bleak, but when it comes to architecture, Kurt is right, and here is the case in terms of sensor clusters. ...

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