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  • Sagantec RSS Feed

    by Published on 05-20-2012 03:00 PM
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    In the world of sub-40nm IC design, as feature size decreases with each new process node, it becomes increasingly difficult to migrate a layout to a new process technology. Too many factors impact manufacturability and yield. At each new process node, to make sure that a given layout is manufacturable and yields well, it is subject to rules that grow in number, type and complexity. Manual migration of a layout from one process technology to another is extremely complex and time-consuming. When an ...
    by Published on 05-08-2012 05:00 PM
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    Adding sophisticated 2D dynamic compaction technology to address 20nm and 14nm challenges. Santa Clara, California – May 3 ,2012 – Sagantec today announced that it has acquired Dutch startup NP-Komplete Technologies BV (Eindhoven, The Netherlands) for its physical design compaction and migration solutions based on a sophisticated 2D dynamic ...
    Published on 05-25-2011 01:43 PM
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    The problem: To move a single lane variable data rate SerDes (serializer-deserializer) from a 65nm process to a 45nm process, achieving a maximum performance of up to 10.3 Gbps. This is a large piece of complex mixed-signal IP with handcrafted analog circuits. Circuit performance and robustness are critical and must be maintained in the migrated implementation.

    The original design consisted of over 30 blocks with a hierarchical device count of around 30,000 (about 200,000 flat).


    After the
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    Published on 05-16-2011 11:57 AM
    1. Categories:
    2. EDA
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    A High-Definition Multimedia Interface (HDMI) IP core was being implemented in an advanced process technology. This fairly large and complex analog mixed-signal (AMS) IP comprising over 130K devices was close to being finalized and shipped to the customer. But many design rules at the foundry were unexpectedly changed from recommended to compulsory, creating hundreds of thousands of violations. It would have taken months to fix all the problems. ...
    by Published on 05-08-2011 02:00 PM
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    The problem: To move dual-port SRAM library and macros from a 40nm process to a 28nm process. In addition to all the changes between two different foundry processes, the 28nm rules are disruptive and incompatible with the previous rules. The memory corecells (foundry-specific) would also need to be completely replaced.

    Current wisdom was that an IP block migration to 28nm was impossible and a complete re-design would be required. As usual, the schedule was very aggressive so a quick migration was really the only feasible option.

    The main changes: There were many changes in design ...