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  • Cadence Design Systems RSS Feed

    by Published on 07-21-2014 08:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/11623-cadencelogo.jpg

    Cadence announced their 2Q results this afternoon. I listened to the conference call.

    You can read all the details of the results in the press release but the big picture is:
    • Revenue $379K, net income $23M GAAP or $64M non-GAAP (8, 21c per share, beat estimates
    ...
    by Published on 07-17-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/11585-protium1.jpg

    Today, Cadence announced Protium, a new FPGA prototyping platform for software development. During development of an SoC, the most appropriate methodology changes. In the early days, developing RTL, the primary tool is simulation. Then, as the blocks get ...
    by Published on 07-14-2014 05:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/11551-quant0.jpg

    Today Cadence announced their next generation extraction solution called Quantus QRC. Actually they are technically announcing it tomorrow, since it is being announced at CDNLive in Korea where it is already Tuesday morning.

    As with the other recently announced tools that end ...
    by Published on 07-02-2014 05:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. Cadence
    content/attachments/11472-uvm_env.jpg

    It goes without saying that VIPs really play a Very Important Part in SoC verification today. It has created a significant semiconductor market segment in the fabless world of SoC and IP design & verification. In order to meet the aggressive time-to-market for IPs and SoCs, itís imperative that readymade VIPs which are proven with latest specifications must be used to accelerate the complex task of verifying SoCs. And that can happen when there are easy methods available ...
    by Published on 07-01-2014 02:45 AM
    1. Categories:
    2. Semiconductor IP,
    3. Cadence
    content/attachments/11463-cdns-complete-pcie-solution.jpg

    I have been alerted by a blog from Moshik Rubin from Cadence: PCI-SIG has finally released the PCIe 4.0 rev 0.3 specification for members' review, on time for the PCI-SIG developers conference last June in Santa Clara. Since the early days of PCI Express in 2005, Denali (at that time, now Cadence) has positioned the PCIe VIP as the first to be released. This aggressive positioning was a part of Denaliís ...
    by Published on 06-26-2014 09:53 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/11437-img_0043.jpg

    Every year at DAC I enjoy making the rounds to see what's new with SPICE circuit simulators, so on June 3rd I met with Xiuya Li and Dan Zhu of Cadence in San Francisco to get an update about their Spectre tool. There's plenty of competition in the SPICE area from Mentor Graphics (Analog FastSPICE, Eldo, ADiT), Synopsys (HSPICE, CustomSim, FineSim) and others.


    ...
    by Published on 06-03-2014 01:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/11240-lbist_types.jpg

    While focus of the semiconductor industry has shifted to DAC in this week and unfortunately I couldnít attend due to some of my management exams, in my spare time I was browsing through some of the webpages of Cadence to check their new offerings (although they have a great list of items to showcase at DAC) and to my pleasure I came across a really interesting, important one for this age of high-end SoCs which ...
    by Published on 05-26-2014 06:19 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/11122-cadence-ip-port-folio.jpg

    I was attending to CDN-Live in Munich last week, so I was expecting Cadence to announce new IP related acquisition like Lip-Bu Tan did last year (Cosmic Circuit, Evatronix and Tensilica). In fact, Lip-Bu was not in Munich and Charlie Huang, SVP Worldwide Field Operations and System & Verification Group, was holding the morning keynotes for Cadence. The announcement of immediate availability of DDR4 PHY IP built ...
    by Published on 05-18-2014 08:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/11063-roles.jpg

    The power integrity (PI) of a system is an extremely important aspect to be looked at all levels - chip, package and PCB for overall reliability of the system. At the PCB level, a DC analysis, usually based on IR drop, must ensure that adequate DC voltage, satisfying all constraints of current density and temperature, is delivered to all active devices mounted on the PCB. Similarly an AC analysis must ensure that proper AC current, satisfying ...
    Published on 05-13-2014 01:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/11021-denali-party-cadence.jpg

    Cadence is excited to bring a full slate of demos, technical presentations, papers, and more to the Design Automation Conference (DAC) June 1-5, 2014, in San Francisco, CA. From our technical experts, youíll learn tips and techniques from areas including low power, mixed signal, advanced nodes, signoff, verification, and IP, to name just a few. Get details.

    First and foremost the food events:

    Cadence, our customers, and our partners will share their expertise and experiences in electronic design during panels and presentations throughout DAC. The luncheons/breakfast ...

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