You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • Cadence Design Systems RSS Feed

    by Published on 04-09-2014 12:23 PM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/10669-arm-cadence.jpg

    The emerging market for IoT and wearable devices are designed with mixed-signal IP that includes: embedded CPU, flash, analogue and radio. EDA and IP companies have recently worked together to allow us to design an MCU with mixed-signal IP blocks more efficiently. This morning I attended a webinar with presenters from ARM and Cadence Design Systems. I've been following ARM more closely after they acquired IP provider Artisan back in 2004.


    ...
    by Published on 03-16-2014 07:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/10448-photo-4-.jpg

    Cadence continues on its quest to be a top semiconductor IP supplier which is a good thing since the semiconductor world now revolves around IP. Cadence CEO Lip-Bu Tan mentioned IP 14 times during his keynote and he was followed by the president of Imagination Technologies and the CEO of recently acquired Tensilica. I was not afforded the slides for these presentations so we will leave it at that for now. I did sneak a quick photo ...
    by Published on 03-13-2014 04:38 PM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. Cadence,
    5. ARM
    content/attachments/10432-cadencearm.jpg

    The biggest market for semiconductors is mobile and an ARM processor is the center of the axle around which it revolves. So everyone in the mobile ecosystem needs to work closely with ARM. At CDNLive earlier this week Cadence and ARM announced that they are deepening their partnership. Most of what they announced makes it a lot easier to use Cadence's products with ARM's without ...
    by Published on 03-10-2014 03:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/10396-mdv_rtl.jpg

    In the current semiconductor design landscape, the design size and complexity of SoCs has grown to large extent with stable tools and technologies that can take care of integrating several IPs together. With that mammoth growth in designs, verification flows are evolving continuously to tackle the verification challenges at various levels. Today, verification is not a single continuous flow; it is being done from several different angles including formal verification; ...
    by Published on 03-05-2014 08:10 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/10351-cadence-allegro-routing.jpg

    The benefits of using EDA software is that it can automate a manual process, like PCB timing closure, saving you both time and engineering effort. This point was demonstrated today as Cadence added new timing-closure automation to their Allegro product family, calling it Allegro TimingVision. On Tuesday I spoke with Hemant Shah of Cadence by phone to learn more about timing closure of PCB designs.


    PCB routing where each color shows different timing margins
    ...
    by Published on 02-24-2014 08:01 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/10200-multi-user-verification-productivity.jpg

    Big SoC designs typically break existing EDA tools and old methodologies, which then give rise to new EDA tools and methodologies out of necessity. Such is the case with the daunting task of verification planning and management where terabytes of data have simply swamped older EDA tools, making them unpleasant and ineffective to use.

    Last week I spoke by phone with John Brennan of Cadence to learn about their decision to develop a totally new EDA tool for SoC verification planning and management. This is a product area familiar to Cadence users with ...
    by Published on 02-17-2014 08:18 AM
    content/attachments/10171-2012-2011-revenues.jpg

    This news is certainly not as amazing that the acquisition of MIPS by Imagination, or Arteris by Qualcomm… but it shows that Cadence is building a complete Interface IP port-folio, brick after brick. The result will be that a complete wall is being built on the Synopsys road to monopoly and complete success on Interface IP market. When evaluating HDMI and DisplayPort IP segment, the two big names are Synopsys and Silicon Image, and Transwitch comes ...
    by Published on 02-11-2014 07:35 PM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor Manufacturers,
    4. Cadence,
    5. TSMC
    content/attachments/10091-finfet-layout-ideal.jpg

    IC designers contemplating the transition to 16nm FinFET technology for their next SoC need to be informed about design flow and IP changes, so TSMC teamed up with Cadence Design Systems today to present a webinar on that topic. I attended the webinar and will summarize my findings.

    Shown below is a 3D layout concept of an ideal FinFET transistor, followed by the actual manufactured device which is rotated 90 degrees from the layout:



    ...
    by Published on 02-06-2014 08:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence
    content/attachments/10054-pic1.jpg

    In the current decade of SoCs, semiconductor design size and complexity has grown by unprecedented scale in terms of gate density, number of IPs, memory blocks, analog and digital content and so on; and yet expected to increase further by many folds. Given that level of design, it’s imperative that SoC verification challenge has gone much beyond that (more than 2/3rd of design time is spent in verification) at an exponential rate; however verification resources have seen more or ...
    by Published on 02-05-2014 02:46 PM
    1. Categories:
    2. Semiconductor Design,
    3. Cadence,
    4. Forte Design Systems
    content/attachments/10050-forte.jpg


    Cadence today announced that it is acquiring Forte Design Systems. Forte was the earliest of the high-level synthesis (HLS) companies. There were earlier products. Synopsys had Behavioral Compiler and Cadence had a product whose name I forget (Visual Architect?), but both products were too early and were canceled. Cadence internally developed their own high-level synthesis product called C-to-Silicon ...

    Page 1 of 15 12311 ... LastLast