Cadence Design Systems

I had time for lunch on Monday. That is to say, there was a Cadence panel session about Has Timing Signoff Innovation has become and Oxymoron? What Happened and How Do We Fix It?

The moderator was Brian Fuller, lately of EE Times but now Editor-in-Chief at Cadence (I'm not sure quite what it means either). On the panel were Dipesh Patel, EVP of Physical IP at ARM; Tom Spyrou, Design Technology Architect at ...

My 8 years as an IC circuit designer were at the transistor-level, so if that interests you as well then consider what there is to see from Cadence at DAC this year. IC design technology is changing quickly, so keeping up to date is important for your job security and continual education goals.



Here's what I would recommend attending at Cadence in Booth #2214: ...

Today Cadence announced Tempus, their new timing signoff solution. This has been in development for at least a couple of years and has been built from the ground up to be massively parallelized. Not just that different corners can be run in parallel (which is basically straightforward) but that large designs can be partitioned across multiple servers too. So Tempus is ...

Cadence is a DAC anchor, everyone will visit their booth, so lets look at their technical sessions and put our agendas together. Lets start with the breakfast/lunch sessions because Cadence usually puts out quite a spread, we all gotta eat and free food tastes even better:

Has “Timing Signoff Innovation” Become an Oxymoron? What Happened and How Do We Fix ...

Design IP, at least Interface IP, is about 15 years old, but the market was made of one large provider - Synopsys- with many small vendors around. Chip makers were not very comfortable with this picture, especially the Tier 1 considering that the risk (to see the big one being acquired by one of their direct competitor, say Samsung or Intel) was unacceptable. This was the picture in 2010: Synopsys leader on every Interface IP segment, Cadence ...

Every process node these days has a new "gotcha" that designers need to be aware of. In some ways this has always been the case but the changes used to be gradual. But now each process node has something discontinuously different. At 20nm the big change is double patterning. At 14/16nm it is FinFET.

Rahul Deokar and John Stabenow of Cadence and Jason Chen from TSMC will ...

It was definitely a good idea to go to Munich to listen to the keynote talk from Lip-Bu Tan. Did I learned in direct live the name of the next acquisition from Cadence in 2013, after Tensilica and Cosmic Circuits? Yes and the winner is… Evatronix! And cadence as well as Evatronix is enjoying more than 600 customers worldwide, thanks to a wide port-folio ranging from 8051 IP core to SuperSpeed ...

Often a question is raised about how SystemC improves verification time when the design has to go through RTL in any case. A simple answer is that with SystemC, designs can be described at a higher level of abstraction and then automatically synthesized to RTL. When the hands-on design and verification activity is at a higher level, there are fewer opportunities to introduce bugs, and it is much easier ...

Going to Munich in May could be a very good idea, as it will give you the opportunity to listen to the keynote talk from Lip-Bu Tan. Who knows if you will learn in direct live the name of the next acquisition from Cadence in 2013, after Tensilica and Cosmic Circuits? In fact, there may not be new acquisition announcement, then this keynote talk should help understanding current Cadence’ strategy for developing IP business. Looking ...