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  • Oasys RSS Feed

    by Published on 10-02-2013 01:45 PM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/8769-7313d1369011487-fp3.jpg

    One area of iteration that is becoming more problematic is between floorplanning and synthesis. So much of timing is driven by placement that fixing timing and even power often involves not just re-synthesis and re-placement but alterations to the floorplan. The Achilles heel of existing methods is that floorplanning tools are forced to use a "fixed netlist" as ...
    by Published on 07-17-2013 02:01 PM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/7956-pie1.jpg

    One challenge in building a modern SoC is that you want to minimize power, performance and area (PPA) while still getting your chip to market on schedule. Realistically, you can't actually minimize all of these at once since they are tradeoffs: speeding up a critical path often involves upsizing drivers to larger cells which obviously has a negative effect on area and ...
    by Published on 06-28-2013 01:07 PM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/7783-img_3491.jpg

    At DAC you can measure buzz by how many people are crowded into your booth. I saw a crowd at the Oasys booth, so stopped to take in their 10 minute overview presentation. Here's what I learned.


    ...
    by Published on 05-19-2013 04:58 PM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/7313-fp3.jpg

    Today Oasys announced the availability of Floorplan Compiler in the Oasys RealTime suite of physical RTL exploration and synthesis tools. This is actually a repackaging of a capability that has always been in RealTime Designer, and in fact has been an important aspect of how well RealTime Designer has performed in benchmarks over the last four ...
    by Published on 05-12-2013 12:41 PM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/7178-gajski-kuhn-y-chart.jpg

    Thirty years ago in 1983 Professor Daniel Gajski and Kuhn created the now famous Y-Chart to show the various levels of abstraction in electronic system design:



    We can still use this Y-Chart today because it still pertains to how engineers are doing their SoC designs. Along the Behavioral axis there is a need to know that each level of abstraction is really equivalent to the other levels to ensure that the design is consistent, ...
    by Published on 03-19-2013 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/6520-retime1.jpg

    I was at the EDAC CEO forecast meeting last week and one of the questions that was asked of EDAC members was "which is the hottest EDA startup?" The one with the most nominations was Oasys. So Oasys is hot.

    But register retiming is hotter.

    The latest announcement from Oasys this morning is that register retiming is now available ...
    by Published on 03-05-2013 12:29 PM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/6360-oasysos.jpg

    Formal verification can be used for many things, but one is to ensure that synthesis performs correctly and that the behavior of the output netlist is the same as the behavior of the input RTL. But designs are getting very large and formal verification is a complex tool to use, especially if the design is too large for the ...
    by Published on 02-13-2013 10:14 AM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/6179-congestion-caused-wide-mux-rtl.jpg

    I read two blogs this week that got me to thinking about contingencies in SoC implementation. By contingency I mean using an EDA tool flow from the leading vendor for logic synthesis and then discovering that you cannot route the design without expanding the die size after a few weeks of concerted effort, then having to come up with a Plan B. The blogs were from two people at Oasys Design Systems:

    ...
    by Published on 01-31-2013 07:05 PM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/6063-tsmc.jpg

    Oasys has joined the TSMC Soft-IP Alliance Program. This means that TSMC IP partners have access to a new RTL exploration tool to improve QoR and reduce the iterations needed for design closure. In modern process nodes, RTL engineers implementing complex IP cores for graphics, networking, and mobile computing ...
    by Published on 01-18-2013 01:21 PM
    1. Categories:
    2. Semiconductor Design,
    3. Oasys
    content/attachments/5952-scottseaton.jpg

    Scott Seaton is the new CEO of Oasys Design Systems. Paul van Besouw, the CEO since the company's founding, becomes the CTO. I met Scott last year when I was doing some consulting work for Carbon Design where he was VP of sales (the new VP sales at Carbon is Hal Conklin, by the way).

    I talked to Scott about why he had joined ...

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