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    by Published on 07-21-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Blendics
    content/attachments/11611-blendics.jpg

    The reliability metric, Mean Time Between Failures (MTBF), is often misunderstood. Use of an MTBF metric generally assumes a random failure process, one that is very infrequent and has no memory of past failures. Such failure modes can occur in System-on-Chip (SoC) designs and ...
    Published on 03-23-2014 08:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Blendics
    content/attachments/10513-car-roof.jpg

    As an example of the need for real-world reliability metrics, consider a modern automobile. We can already buy a car with parking assistance, collision avoidance, autonomous braking and adaptive cruise control features. These new features depend on video image processing that requires high-performance SoC components where multiple clock domains are certain to be required. ...
    by Published on 09-24-2013 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Blendics
    content/attachments/8706-semiwikifig1.jpg

    You may say, ďWhy should I worry about synchronizer failures when I have never seen one fail in a product?Ē Perhaps you feel that the dual-rank synchronizer used by many designers makes your design safe. Furthermore, those chips that have occasional unexpected failures never show any forensic evidence of synchronizer failures. Why worry?
    ...
    by Published on 08-25-2013 08:30 PM
    1. Categories:
    2. Semiconductor Design,
    3. Blendics
    content/attachments/8361-dff-shorted-nodes.jpg

    Estimating the MTBF of an SoC should always include an analysis of synchronizer reliability. Contemporary process nodes are introducing new challenges to the reliability of clock domain crossings so it is prudent to revisit how your simulation tool calculates a synchronizerís MTBF. Letís list the ten most common pitfalls. ...
    by Published on 07-24-2013 06:05 PM
    1. Categories:
    2. Semiconductor Design,
    3. Blendics
    content/attachments/8042-metaaceimg.jpg

    Metastability is a critical SoC failure mode that occurs at the interface between clocked and clockless systems. It's a risk that must be carefully managed as the industry moves to increasingly dense designs at 28nm and below. Blendics is an emerging technology company that I have been working with recently, their MetaACE product can be used throughout the design flow starting with foundation IP.

    For standard cells, there are at least three groups that benefit from MetaACE:

    • The designer
    ...
    by Published on 06-23-2013 06:10 PM
    1. Categories:
    2. Semiconductor Design,
    3. Blendics
    content/attachments/7703-semiwikipart2fig1.jpg

    In Part 1 of this topic I discussed what it takes to estimate the mean time between failures (MTBF) of a single stage synchronizer. Because supply voltages are decreasing and transistor thresholds have been pushed up to minimize leakage, the shortened MTBF of many synchronizer circuits at nanoscale process nodes is presenting an increased risk of failure. ...
    by Published on 06-18-2013 06:30 PM
    1. Categories:
    2. Semiconductor Design,
    3. Blendics
    content/attachments/7653-figure_semiwikimasterslave-1-.jpg

    Recently, I discussed the increasing risk of metastability hazards at nanoscale geometries. These risks are significantly aggravated at low supply voltages and low temperatures and must be addressed during the design cycle of any mission critical application. This time I discuss what it takes to estimate a synchronizerís mean-time between failures (MTBF).

    Some flip-flops do a better job as a synchronizer than others. Sometimes you ...
    by Published on 06-09-2013 01:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Blendics
    content/attachments/7498-figure1.jpg

    Metastability is an inescapable phenomenon in digital electronic systems. This phenomenon has been known to cause fatal system errors for half a century. Over the years, designers have used convenient rules of thumb for designing synchronizers to mitigate it. However, as digital circuits have become more complex, smaller and faster with reduced voltage, these rules of thumb are beginning to fail. A new tool from ...