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  • Concept Engineering GmbH RSS Feed

    by Published on 03-13-2014 02:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    A very popular acronym is ‘WYSIWYG’ – What You See Is What You Get! This is very true and is important to visualize things to make it better in various aspects such as aesthetics, compactness, organization, structure, understandable for correction and so on; the most important, in case of semiconductor design, is being able to identify issues and resolve them to get the best PPA optimized design.

    No matter how complex a design is, designers need to decompose it ...
    by Published on 02-28-2014 05:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly. Considering today’s large SoC designs with multiple IPs, it’s imperative that effective debugging tools with easy and ...
    by Published on 01-23-2014 07:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    When we talk about parasitic, we talk about post layout design further expanded in terms of electrical components such as resistances and capacitances. In the semiconductor design environment where multiple parts of a design from different sources are assembled together into highly complex, high density SoC, imagine how complex it would be to debug that design at parasitic level. We definitely need smart tools to be able to analyse different parts of a design, at different levels of hierarchy, and at different levels ...
    by Published on 12-04-2013 01:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/9418-concept_logo.gif

    In an environment of SoCs with tough targets of multiple functionalities, smallest size, lowest power and fastest performance to achieve within a limited design cycle window in order to meet the rigid time-to-market requirements, any day spent without success becomes very frustrating for a designer. Especially during tape-out time, when the actual layout is ready, every day spent in debugging and resolving issues feels like climbing one large ...
    Published on 12-03-2013 01:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    We cordially invite you to attend this webinar and learn how to quickly debug post layout designs. Concept Engineering is a privately held company based in Freiburg, Germany. It was, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design ...
    by Published on 07-16-2013 06:29 PM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/7947-starvision-pro.jpg

    When looking at the time to design and verify an SoC we've known for many years now that the verification effort requires more time than the design process. So anything that will shorten the verification effort will have the biggest impact on keeping your project on schedule.

    A second trend is the amount of Analog content in a mostly Digital SoC, which further complicates the verification process because analog IP is created ...
    by Published on 06-24-2013 02:07 PM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/7718-img_3461.jpg

    If you're involved with AMS or transistor-level IC design then having visual tools will help you design and debug quicker. At DAC I met with Gerhard Angst, President and Founder of Concept Engineering to get an update.


    Gerhard Angst (center), Concept Engineering

    ...
    by Published on 06-09-2013 06:05 PM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/7328-rns.jpg

    I'm utterly amazed at how IC-based products are improving our quality of life by implantable devices. The modern day pacemaker has given people added years of life by electrically stimulating the heart. A privately-held company called NeuroPace was founded in Mountain View, California to treat epilepsy by using responsive neurostimulation. Their first product is called the RNS System (Responsive NeuroStimulation), and it is a programmable, battery-powered, microprocessor-controlled device that delivers a short train of electrical pulses to the brain through implanted leads.



    I spoke with Dean Anderson, ...
    by Published on 05-29-2013 08:53 AM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/7434-parasitic-netlist-exploration-1.jpg

    Debugging an IC design at the transistor, Gate and RTL levels is often necessary to meet timing requirements and understand analog or digital behavior, yet the process itself can be a tedious one, filled with manual steps, therefore making it an error-prone process. EDA tools have been created to help us graphically debug transistor, Gate and RTL designs, and one company called Concept Engineering is appearing at DAC again this year in Austin to showcase many incremental improvements to their ...
    by Published on 04-05-2013 11:22 AM
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/6677-sucharita-biswas.jpg

    My background is IC design engineering, so it's always a delight to talk with another engineer on their chip challenges. Today I spoke by phone with Sucharita Biswas, a Senior Hardware Engineer at Altera involved in IC test debug for FPGA devices.


    ...

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