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  • Concept Engineering GmbH RSS Feed

    by Published on 07-07-2014 06:30 AM  Number of Views: 704 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    As the semiconductor design community is seeing higher and higher levels of abstraction with standard IPs and other complex, customized IPs and sub-systems integrated together at the system level, sooner than later we will find SoCs to be just assemblies of numerous IPs selected off-the-self according to the design needs and specifications. Does that sound so simple? No, it’s harder than we can think of. A major ...
    by Published on 05-15-2014 08:00 PM  Number of Views: 693 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    In a complex environment of semiconductor design where an SoC can have several millions of gates and multiple number of IPs at different levels of abstractions from different sources integrated together, it becomes really difficult to understand and debug the overall SoC design. Of course, along with the SoC integration, optimization of the overall design in terms of timing, power ...
    by Published on 04-21-2014 06:00 PM  Number of Views: 1293 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/10791-cone_view.jpg

    In a complex world of SoCs with multi-million gates and IPs from several heterogeneous sources, verification of a complete semiconductor design has become extremely difficult, and it’s not enough. In order to ascertain the right intent of the design throughout the design cycle, debugging at various stages of the design cycle has to go hand-in-hand along with the design and verification; the architect of the design should be able to make expert judgement and take appropriate action before a small weakness in the design ...
    by Published on 04-16-2014 02:30 PM  Number of Views: 925 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    In EDA arena we often find companies providing customization platforms along with the tools they offer to their customers. I admire such companies because they equip the end users of a tool to extend its functionality as they like according to their environment, thus increasing the designer productivity significantly. And I’m witness to some expert creative users of Cadence tools, during my job at Cadence, who made very powerful customized tools based on the SKILL scripting. What reminded me about ...
    by Published on 03-13-2014 02:30 AM  Number of Views: 695 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/10417-spice.jpg

    A very popular acronym is ‘WYSIWYG’ – What You See Is What You Get! This is very true and is important to visualize things to make it better in various aspects such as aesthetics, compactness, organization, structure, understandable for correction and so on; the most important, in case of semiconductor design, is being able to identify issues and resolve them to get the best PPA optimized design.

    No matter how complex a design is, designers need to decompose it ...
    by Published on 02-28-2014 05:30 AM  Number of Views: 1146 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/10299-mixed_source.jpg

    A semiconductor SoC design can have multiple components at different levels of abstractions from different sources and in different languages. While designing an SoC, IPs at different levels have to be integrated without losing the overall design goals. Of course, quality of an IP inside and outside of an SoC must be tested thoroughly. Considering today’s large SoC designs with multiple IPs, it’s imperative that effective debugging tools with easy and ...
    by Published on 01-23-2014 07:00 AM  Number of Views: 5015 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/9870-views.jpg

    When we talk about parasitic, we talk about post layout design further expanded in terms of electrical components such as resistances and capacitances. In the semiconductor design environment where multiple parts of a design from different sources are assembled together into highly complex, high density SoC, imagine how complex it would be to debug that design at parasitic level. We definitely need smart tools to be able to analyse different parts of a design, at different levels of hierarchy, and at different levels ...
    by Published on 12-04-2013 01:00 PM  Number of Views: 1420 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    In an environment of SoCs with tough targets of multiple functionalities, smallest size, lowest power and fastest performance to achieve within a limited design cycle window in order to meet the rigid time-to-market requirements, any day spent without success becomes very frustrating for a designer. Especially during tape-out time, when the actual layout is ready, every day spent in debugging and resolving issues feels like climbing one large ...
    Published on 12-03-2013 01:00 PM  Number of Views: 951 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
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    We cordially invite you to attend this webinar and learn how to quickly debug post layout designs. Concept Engineering is a privately held company based in Freiburg, Germany. It was, founded in 1990 to develop and market innovative schematic generation and viewing technology for use with logic synthesis, verification, test automation and physical design ...
    by Published on 07-16-2013 06:29 PM  Number of Views: 1483 
    1. Categories:
    2. Semiconductor Design,
    3. Concept Engineering
    content/attachments/7947-starvision-pro.jpg

    When looking at the time to design and verify an SoC we've known for many years now that the verification effort requires more time than the design process. So anything that will shorten the verification effort will have the biggest impact on keeping your project on schedule.

    A second trend is the amount of Analog content in a mostly Digital SoC, which further complicates the verification process because analog IP is created ...

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