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  • IROC Technologies RSS Feed

    by Published on 09-09-2013 12:34 PM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies,
    4. TSMC
    content/attachments/8530-irt1.jpg

    Increasingly, end users in some markets are requiring soft error rate (SER) data. This is a measure of how resistant the design (library, chip, system) is to single event effects (SEE). These manifest themselves as SEU (upset), SET (transient), SEL (latch-up), SEFI (functional interrupt).

    There are two main sources that cause these SEE:
    • natural atmospheric neutrons
    • alpha particles

    ...
    by Published on 08-13-2013 12:01 PM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies
    content/attachments/8209-tfit.jpg

    There are two ways to see how resistant your designs are to single-event errors (SEE). One is to take the chip or even the entire system and put it in a neutron beam and measure how many problems occur in this extreme environment. While that may be a necessary part of qualification in some very high reliability situations, it is also ...
    by Published on 07-25-2013 11:09 AM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies
    content/attachments/8065-iroc2.jpg

    How reliable is your cell-phone? Actually, you don't really care. It will crash from time to time due to software bugs and you'll throw it away after two or three years. If a few phones also crash due to stray neutrons from outer space or stray alpha particles from the solder balls used in the flip-chip bonding then nobody cares.

    How about your heart pacemaker? Or the braking system in ...
    by Published on 06-12-2013 08:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies
    content/attachments/7579-file1-adrian.jpg

    As we have moved towards extremely low process nodes with very high chip density, the cost of mask preparation also has become exorbitantly high. It has become essential to know about the failure rates and mitigate the same at the design time before chip fabrication, and also to make sure about chip reliability over time as it is constantly exposed under cosmic rays and natural environment of radiation. Chip failure due to soft ...
    by Published on 05-26-2013 07:10 PM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies
    content/attachments/7297-dan-iroc.jpg

    One of the best things about being part of SemiWiki is the exposure to new technologies and the people behind them. SemiWiki now works with more than 35 companies and I get to spend time with each and every one of them. Much like I do, IROC Technologies works closely with the foundries and the top semiconductor companies so it was a pleasure to do this CEO interview:

    Q: What are the specific design challenges your customers are facing?

    A: The design flow is an always evolving, ...
    by Published on 05-22-2013 05:51 PM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies
    content/attachments/7353-irw1.jpg

    As we get down to smaller and smaller process nodes, the problem of soft errors becomes increasingly important. These soft errors are caused by neutrons from cosmic rays, alpha particles from materials used in manufacture and other sources. For chips that go into systems with high reliability this is not something that can be ignored. Everyone ...
    by Published on 05-13-2013 01:50 PM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies
    content/attachments/7219-socfit1.jpg

    I blogged recently about reliability testing with high energy neutron beams. This is good for getting basic reliability data but it is not really a useful tool for worrying about reliability while the chip is still being designed and something can be done about it.

    That is where IROC Technologies SOCFIT tool comes in. It takes all the data from the type of ...
    by Published on 05-06-2013 02:49 PM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies
    content/attachments/7086-neutrons.jpg

    So you want to know how reliable your chips are and how susceptible they are to single event effects (SEEs) where a neutron or an alpha particle causes a storage element (flop or memory cell) to flip in a way that alters the behavior of the device. There are two ways a particle hitting a device might not cause a problem. Firstly, the particle might hit an area of the chip that is not vulnerable to ...
    by Published on 04-03-2013 05:06 PM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies
    content/attachments/6665-tfit2.jpg

    I blogged last month about single event effects (SEE) where a semiconductor chip behaves incorrectly due to being hit by an ion or a neutron. Since we live on a radioactive planet and are bombarded by cosmic rays from space, this is a real problem, and it is getting worse at each process node. But just how big of a problem is it?


    TFIT is a tool for ...
    by Published on 03-09-2013 08:56 AM
    1. Categories:
    2. Semiconductor Design,
    3. IROC Technologies
    content/attachments/6412-iroc22.jpg

    It has be come a cliche to say that "power is the new timing", the thing that keeps designers up at night and drives the major architectural decisions in big SoCs. Nobody is saying it yet but perhaps "reliability is the new power" will be tomorrow's received wisdom.

    I talked to Adrian Evans of IROCTech last week. He used to work at Cisco and with an enormous installed base ...

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