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    High Yield and Performance - How to Assure? 

    by
    Pawan Fangaria
    Published on 04-16-2012 05:30 AM
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    In today’s era, high performance mobile devices are asserting their place in every gizmos we play with and guess what enables them work efficiently behind the scene – it’s large chunks of memory with low power and high speed, packed as dense as possible. Ever growing requirement of power, performance and area led us to process nodes like 20nm, but that has a burgeoning challenge of extreme process variation limiting the yield. However there is no escape from detecting the failure rate early in the cycle to assure high yield.

    In case of memory, there ...
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    A Survey of High-Sigma Monte Carlo Analysis Approaches 

    by
    Guest Blogger
    Published on 03-04-2012 01:00 PM
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    This article reviews the problem of high-sigma analysis, then various approaches such as Monte Carlo, Importance Sampling, linear / Worst-Case Distance, and High-Sigma Monte Carlo.
    ...
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    High-efficiency PVT and Monte Carlo analysis in the TSMC AMS Reference Flow for optimal yield in memory, analog and digital design! 

    by
    Daniel Nenni
    Published on 11-01-2011 07:00 AM
    1. Categories:
    2. Solido
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    Hello Daniel,
    I am very interested on the articles on the PVT simulation, I have worked in that area in the past when I worked in process technology development and spice modeling and I also started a company called Device modeling technology (DMT) which built a Spice model library of discrete components, such as Bipolar/MOS /POWER MOSFET/Analog Switch/ADC/CDA/PLL sold to companies like Fujitsu, Toshiba ...etc.

    We used to have a project when I worked     ...
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    Solido & TSMC Variation Webinar for Optimal Yield in Memory, Analog, Custom Digital Design 

    by
    Daniel Nenni
    Published on 10-09-2011 02:01 PM
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    Solido has announced webinars for North America, Europe and Asia on October 12-13. They will be describing the variation analysis and design solutions in the TSMC AMS Reference Flow 2.0 announced at the Design Automation Conference this year.

    “We are pleased to broaden our collaboration with Solido in developing advanced variation and design methodology in AMS Reference Flow 2.0. TSMC ...
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    PVT and Statistical Design in Nanometer Process Geometries 

    by
    Daniel Nenni
    Published on 09-18-2011 07:00 AM
    1. Categories:
    2. EDA
    content/attachments/1875-image1_pvt-flow.jpg.html

    On Sept 22, 2011, the nm Circuit Verification Forum will be held in Silicon Valley, hosted by Berkeley Design Automation. At this forum, Trent McConaghy of Solido DA will present a case study on the TSMC Reference Flow 2.0 VCO circuit, to showcase Fast PVT in the steps of extracting PVT corners, verifying PVT, and doing post-layout PVT verification. The presentation will cover the speed benefit of Solido Fast PVT, and the multiplicative ...
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    Semiconductor Yield @ 28nm HKMG! 

    by
    Daniel Nenni
    Published on 08-28-2011 02:00 PM
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    Whether you use a gate-first or gate-last High-k Metal Gate implementation, yield will be your #1 concern at 28nm, which makes variation analysis and verification a big challenge. One of the consulting projects I have been working on with the foundries and top fabless semiconductor companies is High-Sigma Monte Carlo (HSMC) verification technologies. It has been a bumpy two years certainly, but the results make for a good blog so I expect this one will be well read.
    ...
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    Solido - Variation Analysis and Design Software for Custom ICs 

    by
    daniel_payne
    Published on 08-15-2011 05:11 PM
    1. Categories:
    2. EDA,
    3. Solido
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    Introduction
    When I designed DRAM chips at Intel I wanted to simulate at the worst case process corners to help make my design as robust as possible in order to improve yields. My manager knew what the worst case corners were based on years of prior experience, so that's what I used for my circuit simulations.

    Today it's not so intuitive what the worst case process corners are for each specific IC design, so you could just use brute force Monte-Carlo simulations to find them. This approach takes a massive amount of time, CPUs and SPICE licenses. There has to be a better way.

    Variation Analysis at DAC
    My DAC schedule got completely filled this year on Sunday thru Wednesday, so I didn't get to hear from Solido about what's new. As soon as DAC ended and I blogged my trip reports I soon heard from Solido, so we scheduled some time in July to review what they presented at DAC in San Diego.

    I spoke by phone with Kris ...
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