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  • Solido Design Automation RSS Feed

    by Published on 10-03-2013 09:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Solido DA
    content/attachments/8788-solido-high-sigma-standard-cell-optimization.jpg

    Standard cell optimization is an important problem, because the speed, power, and area of cells has a direct impact speed, power, and area of the whole chip. Typically, standard cell optimization been done with simple in-house local-optimizer scripts. However, these optimizers have had several flaws: they don’t properly capture the variation, they get stuck in local optima, and they are serial and ...
    by Published on 09-20-2013 09:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Solido DA
    content/attachments/8670-solido-variation-designer-3.0.jpg

    With the insatiable wafer appetites of the fabless semiconductor companies in the mobile space, yield has never been more critical. The result being better EDA tools every year and this blog highlights one of the many examples. It has been a pleasure writing about Solido Design Automation and seeing them succeed amongst the foundries and their top customers. Here is a Q&A with Amit Gupta, president & CEO of Solido, to get more details on the new Solido Variation Designer 3.0 release:

    Q: What is Solido Variation Designer used for?

    Solido Variation Designer is variation analysis and design software for custom ICs. Our users run Variation ...
    by Published on 05-18-2013 02:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Solido DA
    content/attachments/7301-analyze-mismatch.jpg

    One of the places you will be able to find me at the Design Automation Conference (DAC) is on the speaker panel for a Monday Tutorial – Winning in Monte Carlo: Managing Simulations Under Variability and Reliability. Having worked closely with TSMC, GLOBALFOUNDRIES, Solido Design Automation, and some of the top fabless semiconductor companies, I have first hand experience with the increased variation at advanced process nodes and the increased SPICE ...
    by Published on 05-11-2013 05:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Solido DA
    content/attachments/7196-solido-book-process-variation.jpg

    I recently talked to Trent McConaghy about his book on variation-aware design of custom ICs and the #50DAC tutorial we are doing:

    Winning in Monte Carlo: Managing Simulations Under Variability and Reliability
    .

    Trent is the Solido Chief Technology Officer, an engaging speaker, one of the brightest minds in EDA, and someone who I have thoroughly enjoyed working with for the past three years.

    Topic Area: Design for Manufacturability
    Date: Monday, June 3, 2013
    Time: 11:00 ...
    by Published on 05-04-2013 09:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor Manufacturers,
    4. Solido DA,
    5. GlobalFoundries,
    6. TSMC
    content/attachments/6956-amit-solido.jpg

    EDA needs more CEOs like Amit Gupta. Solido, which is now profitable, is his second AMS EDA company. The first, Analog Design Automation (ADA), was purchased by Synopsys for a hefty multiplier. Prior to becoming an EDA entrepreneur, Amit was product manager for the wireless group at Nortel and a hardware engineer for the RF communications group at Harris Corporation. I like the Q&A blogs Daniel and Paul do on SemiWiki so here is my first one:

    Q: What are the specific custom IC design challenges your customers ...
    by Published on 04-27-2013 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor Manufacturers,
    4. Solido DA,
    5. TSMC
    content/attachments/6942-variation-designer-platform.jpg

    Process variation has been a top trending term since SemiWiki began as a result of the articles, wikis, and white papers posted on the Solido landing page. Last year Solido and TSMC did a webinar together, an article in EETimes, and Solido released a book on the subject. Process variation is a challenge today at 28nm and it gets worse at 20nm and 16nm so you had better be ready.

    Solido and TSMC recently completed qualification of Solido Variation Designer for 20-nm ...
    by Published on 12-01-2012 12:57 PM
    1. Categories:
    2. Semiconductor Design,
    3. Solido DA
    content/attachments/5538-screen-shot-2012-12-01-1.01.50-pm.jpg

    IC designers using advanced nodes are acutely aware of how variation effects in the silicon itself are causing increased analysis and design efforts in order to yield chips at acceptable levels. Four authors from Solido are so passionate about this topic that they combined their years of experience into a book that I had a chance to read and review. Analog, AMS and even high-speed digital designers would benefit from the design ideas suggested in this book. I will give away one free copy of this book (retail value $120.00) to the person who comments on the blog with the best request.

    ...
    by Published on 11-06-2012 06:30 PM
    1. Categories:
    2. Semiconductor Design,
    3. Solido DA
    content/attachments/5363-memoryplus-flow.jpg

    Solido Design Automation and TSMC recently published an article in EE Times describing how Solido’s High-Sigma Monte Carlo tool is used with TSMC PDK’s to achieve high-yield, high-performance memory design. This project has been a big part of my life for the past three years and it is time for a victory lap!

    In TSMC 28nm, 20nm and smaller process nodes, achieving target yields is extremely challenging. Nowhere is this truer than for memory circuits, which aggressively adopt next bleeding-edge ...
    by Published on 11-01-2012 08:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Solido DA
    content/attachments/5323-deeplogo_c.jpg


    There is an interesting 6 sigma verification discussion on DeepChip today. I have worked with Solido for the past three years so I was alerted to it by multiple people. In fact, 6 Sigma Verification is the reason why I wanted to work with Solido. In the EDA world of “nice to have" point tools 6 sigma verification is a “gotta have” which is much more fun to work with.

    By discussion on DeepChip what I really mean is John Cooley editing and posting comments when he gets around to it. The first so called ...
    by Published on 06-21-2012 06:15 PM
    1. Categories:
    2. Semiconductor Design,
    3. Solido DA
    content/attachments/4127-2012-06-05-18.11.04.jpg

    I met with Amit Gupta, President and CEO of Solido at DAC on Tuesday to get an update on their EDA tools used in the design of memory, standard cells and low-power. In 2012 they've expanded to add three new software packages: Memory, Standard Cell, Low Power. They must be doing something right because at DAC this year I see more competitors jumping into the Fast Monte Carlo space. ...

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