Solido Design Automation

EDA needs more CEOs like Amit Gupta. Solido, which is now profitable, is his second AMS EDA company. The first, Analog Design Automation (ADA), was purchased by Synopsys for a hefty multiplier. Prior to becoming an EDA entrepreneur, Amit was product manager for the wireless group at Nortel and a hardware engineer for the RF communications group at Harris Corporation. I like the Q&A blogs Daniel and Paul do on SemiWiki so here is my first one:

Q: What are the specific custom IC design challenges your customers ...

Process variation has been a top trending term since SemiWiki began as a result of the articles, wikis, and white papers posted on the Solido landing page. Last year Solido and TSMC did a webinar together, an article in EETimes, and Solido released a book on the subject. Process variation is a challenge today at 28nm and it gets worse at 20nm and 16nm so you had better be ready.

Solido and TSMC recently completed qualification of Solido Variation Designer for 20-nm ...

IC designers using advanced nodes are acutely aware of how variation effects in the silicon itself are causing increased analysis and design efforts in order to yield chips at acceptable levels. Four authors from Solido are so passionate about this topic that they combined their years of experience into a book that I had a chance to read and review. Analog, AMS and even high-speed digital designers would benefit from the design ideas suggested in this book. I will give away one free copy of this book (retail value $120.00) to the person who comments on the blog with the best request.

...

Solido Design Automation and TSMC recently published an article in EE Times describing how Solido’s High-Sigma Monte Carlo tool is used with TSMC PDK’s to achieve high-yield, high-performance memory design. This project has been a big part of my life for the past three years and it is time for a victory lap!

In TSMC 28nm, 20nm and smaller process nodes, achieving target yields is extremely challenging. Nowhere is this truer than for memory circuits, which aggressively adopt next bleeding-edge ...

There is an interesting 6 sigma verification discussion on DeepChip today. I have worked with Solido for the past three years so I was alerted to it by multiple people. In fact, 6 Sigma Verification is the reason why I wanted to work with Solido. In the EDA world of “nice to have" point tools 6 sigma verification is a “gotta have” which is much more fun to work with.

By discussion on DeepChip what I really mean is John Cooley editing and posting comments when he gets around to it. The first so called ...

I met with Amit Gupta, President and CEO of Solido at DAC on Tuesday to get an update on their EDA tools used in the design of memory, standard cells and low-power. In 2012 they've expanded to add three new software packages: Memory, Standard Cell, Low Power. They must be doing something right because at DAC this year I see more competitors jumping into the Fast Monte Carlo space. ...

For a small company, Solido has some very large customers and partners, TSMC being on of them. Why? Because of the high yield and memory performance demand on leading edge technologies, that's why.

Much has been made of and will continue to be said on the march of Moore’s Law. While economics of scale and performance vs. power are the main justifications, there ...

Having spent a considerable amount of time with Solido, they were one of the founding members of SemiWiki, I can tell you that at 20nm the Variation Designer Platform is a critical part of the emerging 20nm design methodology. You can read more on Solido's SemiWiki landing page HERE. It is well worth the click.

With technology rapidly going mobile, ...

In today’s era, high performance mobile devices are asserting their place in every gizmos we play with and guess what enables them work efficiently behind the scene – it’s large chunks of memory with low power and high speed, packed as dense as possible. Ever growing requirement of power, performance and area led us to process nodes like 20nm, but that has a burgeoning challenge of extreme process variation limiting the yield. However there is no escape from detecting the failure rate early in the cycle to assure high yield.

In case of memory, there ...