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  • Calypto RSS Feed

    by Published on 03-05-2014 08:37 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/10372-catapult.jpg

    At DVCon today I talked to Sanjiv Kaul, the CEO of Calypto. Just as a reminder, Calypto have 3 products, SLEC (sequential logical equivalence checking, also called sequential formal verification), PowerPro (sequential RTL level power reduction) and Catapult High Level Synthesis (that they took over from Mentor in 2011 in a complicated deal involving stock, people, products and cash). ...
    by Published on 12-20-2013 01:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/9576-cslec2.jpg

    One of the questions that Calypto is asked all the time is what is the difference between sequential logical equivalence checking (SLEC) and logical equivalence checking (LEC).

    LEC is the type of equivalence checking that has been around for 20 years, although like all EDA technologies gradually getting more powerful. LEC is typically used to verify that a netlist implementation ...
    by Published on 11-03-2013 02:30 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/9102-cw1.jpg

    Major power reductions are possible by reducing power at the RTL and system levels, and not just at the gate and physical level. In fact, as is so often the case in design, changes can have much more impact when done at the higher level, even given that at that point in the design there is less accurate feedback about changes. Later the impact of a change is known much more accurately but the difference any change can make is smaller. ...
    by Published on 10-16-2013 06:23 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/8888-calweb.jpg

    One of the benefits of using high-level synthesis is obviously the ease of writing some algorithms in SystemC since it is at a higher level than RTL (thatís why we call it high-level synthesis!). But a second benefit is at the verification level. Since a lot of the verification gets done at the SystemC level, less needs to be done at the RTL level. ...
    by Published on 09-09-2013 12:25 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/8535-sc_top1.gif

    As more people adopt high-level synthesis (HLS) they start to worry about what is the best design flow to be using. This is especially so for verification since it forms such a large part of the effort on a modern SoC. The more people rely on HLS for producing their RTL from C, the more they realize they had better do a good job of verifying the C code in the first ...
    by Published on 08-07-2013 10:42 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/8157-caly1.jpg

    Of course if you are in the business of selling high-level synthesis (HLS) tools then the obvious answer is immediately. Start at 9am tomorrow morning. But a more realistic answer is when you are having to do something completely new. If you are working on a legacy design, perhaps with pre-existing IP, then moving the design up to a higher-level might make ...
    by Published on 07-05-2013 03:48 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/7871-cal131.jpg

    Each year Calypto runs a survey of end-users. This year's survey and report has two parts, power reduction and high level synthesis (HLS).

    The topics covered are:
    • survey methodology and demographics
    • top methods used to reduce power
    • engineering time spent on specfiic RTL tasks to reduce power
    • plans to deploy RTL power reduction tools in 2013
    • methods to
    ...
    by Published on 05-28-2013 08:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/7401-calypto-pic.jpg

    This year for DAC, Calypto has assembled an impressive lineup of customer presentation, suite sessions and Designer Tracks. To start with customer presentation, Steve Kommrusch, Fellow Design Engineer from AMD will be giving a talk in the Calypto Suite on AMDís methodology for low power and will show how AMD was able to get further 20% power reduction on a SoC that was already optimized for low power. ...
    by Published on 05-16-2013 02:12 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/7273-camd1.jpg

    Steve Kommrusch of AMD wrote a white paper with Calypto on how AMD reduced power by 20% on the Jaguar SoC using Calypto's PowerPro. Dan Nenni blogged about it on SemiWiki back in February here. And now, drumroll, Steve will present the story live and in person at DAC, on Monday June 3rd at 3pm and on Wednesday June 5th at 11am. This is a private suite presentation ...
    by Published on 05-11-2013 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/7174-beatles.jpg

    As Julius Caesar said, "Gallia est omnis divisa in partes tres." All Gaul is divided into 3 parts. Calypto is similar with three product lines that work together to provide a system level approach to SoC design. Two of those product lines are not unique, in the sense that similar capabilities are available from a handful of other companies, but the original ...

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