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  • Calypto RSS Feed

    by Published on 11-20-2014 09:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/12599-hls_ver_flow.jpg

    For about a decade I am looking forward to seeing more of system level design and verification including high level synthesis (HLS), virtual prototyping, and system modeling etc. to come in the main stream of SoC design. Although ...
    by Published on 10-27-2014 09:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/12350-verification1.jpg

    Very recently, I was seeing intense discussions on the need for agile hardware development just like agile software and ideas were being sought from experts as well as individuals. While in software world it has already evolved, in hardware world itís yet to see the shift in paradigm. My point is that the ...
    by Published on 09-22-2014 12:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/12077-sanjiv-narayan-2.jpg

    When we get the notion of expansion of a company, it always provides a positive picture about something good happening to boost that expansion. There can be several reasons for expansion such as merger & acquisition, formation of joint venture or partnership, large customer orders ...
    by Published on 09-17-2014 08:05 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/12038-filter.jpg

    With the advent of HLS tools, general notion which comes to mind is that okay, thereís an automated tool which can optimize your design description written in C++/SystemC and provide you a perfect RTL. In real life, itís not so, any design description needs hardware designerís expertise to adopt right algorithm and architecture ...
    by Published on 08-16-2014 07:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11832-seq_clk_gating.jpg

    Of course that reduction has to stay throughout the design cycle up to layout implementation and fabrication. Since the advent of high density, mega functionality SoC designs at advanced nodes and battery life critical devices played by our fingertips, the gap between SoC power requirement and actual SoC power has only increased. ...
    by Published on 07-28-2014 02:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11668-catapult_platform.jpg

    Once upon a time there was a struggle for verification completion of semiconductor designs at gate level. Today, beyond imagination, there is a struggle to verify a design with billions of gates at the RTL level which may never complete. The designs are large ...
    by Published on 06-27-2014 07:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11441-mark-milligan.jpg

    Every since Synopsys dominated the logic synthesis market in the 1980's we've had something called HLS - High Level Synthesis, meaning something higher than what Design Compiler can understand as input. At DAC this year I met with Mark Milligan of Calypto to get an update on what's new with HLS. I first met Mark when he was at Sunrise Test Systems in the 1990's and I was at Viewlogic, so I've kept in touch with him over the years.



    ...
    by Published on 05-27-2014 11:07 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11141-caly1.jpg

    I talked to Mark Milligan this morning, who has just joined Calypto as VP Marketing. I first met Mark back when he was at CoWare and I was at VaST or maybe it was Virtutech. Then he moved on and ran marketing at SpringSoft which, I'm sure you remember, Synopsys acquired. I asked him what encouraged him to join Calypto.

    He said that there is a lot of technology that has been brewing ...
    Published on 05-16-2014 06:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11054-google-calypto-51dac.jpg

    DAC 2014 in San Francisco promises plenty of new information on emerging low power techniques and faster ways to get to working, fully verified RTL using high level synthesis and formal verification. Get the latest from the industry leader in technologies for high level design and verification and low power RTL design by attending our sessions at DAC. These in-depth presentations and demos by our engineers will demonstrate solutions for designers to ...
    by Published on 03-05-2014 09:37 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/10372-catapult.jpg

    At DVCon today I talked to Sanjiv Kaul, the CEO of Calypto. Just as a reminder, Calypto have 3 products, SLEC (sequential logical equivalence checking, also called sequential formal verification), PowerPro (sequential RTL level power reduction) and Catapult High Level Synthesis (that they took over from Mentor in 2011 in a complicated deal involving stock, people, products and cash). ...

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