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    by Published on 08-16-2014 06:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11832-seq_clk_gating.jpg

    Of course that reduction has to stay throughout the design cycle up to layout implementation and fabrication. Since the advent of high density, mega functionality SoC designs at advanced nodes and battery life critical devices played by our fingertips, the gap between SoC power requirement and actual SoC power has only increased. ...
    by Published on 07-28-2014 01:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11668-catapult_platform.jpg

    Once upon a time there was a struggle for verification completion of semiconductor designs at gate level. Today, beyond imagination, there is a struggle to verify a design with billions of gates at the RTL level which may never complete. The designs are large ...
    by Published on 06-27-2014 06:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11441-mark-milligan.jpg

    Every since Synopsys dominated the logic synthesis market in the 1980's we've had something called HLS - High Level Synthesis, meaning something higher than what Design Compiler can understand as input. At DAC this year I met with Mark Milligan of Calypto to get an update on what's new with HLS. I first met Mark when he was at Sunrise Test Systems in the 1990's and I was at Viewlogic, so I've kept in touch with him over the years.



    ...
    by Published on 05-27-2014 10:07 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11141-caly1.jpg

    I talked to Mark Milligan this morning, who has just joined Calypto as VP Marketing. I first met Mark back when he was at CoWare and I was at VaST or maybe it was Virtutech. Then he moved on and ran marketing at SpringSoft which, I'm sure you remember, Synopsys acquired. I asked him what encouraged him to join Calypto.

    He said that there is a lot of technology that has been brewing ...
    Published on 05-16-2014 05:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/11054-google-calypto-51dac.jpg

    DAC 2014 in San Francisco promises plenty of new information on emerging low power techniques and faster ways to get to working, fully verified RTL using high level synthesis and formal verification. Get the latest from the industry leader in technologies for high level design and verification and low power RTL design by attending our sessions at DAC. These in-depth presentations and demos by our engineers will demonstrate solutions for designers to ...
    by Published on 03-05-2014 08:37 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/10372-catapult.jpg

    At DVCon today I talked to Sanjiv Kaul, the CEO of Calypto. Just as a reminder, Calypto have 3 products, SLEC (sequential logical equivalence checking, also called sequential formal verification), PowerPro (sequential RTL level power reduction) and Catapult High Level Synthesis (that they took over from Mentor in 2011 in a complicated deal involving stock, people, products and cash). ...
    by Published on 12-20-2013 01:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/9576-cslec2.jpg

    One of the questions that Calypto is asked all the time is what is the difference between sequential logical equivalence checking (SLEC) and logical equivalence checking (LEC).

    LEC is the type of equivalence checking that has been around for 20 years, although like all EDA technologies gradually getting more powerful. LEC is typically used to verify that a netlist implementation ...
    by Published on 11-03-2013 02:30 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/9102-cw1.jpg

    Major power reductions are possible by reducing power at the RTL and system levels, and not just at the gate and physical level. In fact, as is so often the case in design, changes can have much more impact when done at the higher level, even given that at that point in the design there is less accurate feedback about changes. Later the impact of a change is known much more accurately but the difference any change can make is smaller. ...
    by Published on 10-16-2013 06:23 AM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/8888-calweb.jpg

    One of the benefits of using high-level synthesis is obviously the ease of writing some algorithms in SystemC since it is at a higher level than RTL (thatís why we call it high-level synthesis!). But a second benefit is at the verification level. Since a lot of the verification gets done at the SystemC level, less needs to be done at the RTL level. ...
    by Published on 09-09-2013 12:25 PM
    1. Categories:
    2. Semiconductor Design,
    3. Calypto
    content/attachments/8535-sc_top1.gif

    As more people adopt high-level synthesis (HLS) they start to worry about what is the best design flow to be using. This is especially so for verification since it forms such a large part of the effort on a modern SoC. The more people rely on HLS for producing their RTL from C, the more they realize they had better do a good job of verifying the C code in the first ...

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