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  • Atrenta RSS Feed

    by Published on 07-31-2014 12:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11714-bugscope.jpg

    The last graphics chip that I worked on at Intel was functionally simulated with only a tiny display size of 16x16 pixels, because that size allowed a complete regression test to be simulated overnight. Our team designed three major IP blocks: Display Processor, Graphics Processor and Bus Interface Unit. We wanted to also integrate an 80186 core, ...
    by Published on 07-05-2014 10:20 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11497-semico-research.jpg

    Blogger Pawan Fangaria wrote about Clock Domain Crossing (CDC) a few weeks ago, and so I followed up tonight and watched a webinar about CDC presented by Ravindra Aneja of Atrenta. An RTL design engineer would ultimately want a CDC verification tool that offers:

    • Fast throughput and thoroughness
    • Ability to debug and fix the source of CDC errors
    • Handle billions of gates and be considered a signoff tool

    ...
    by Published on 06-30-2014 05:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11455-piyush-sancheti.jpg

    In the early days of Customer Owned Tooling (COT) the signoff was done at the GDS II, or physical level. Today, however we see the trend of RTL signoff instead because of the EDA tools and methodology available. At DAC earlier this month I met with Piyush Sancheti of Atrenta to get an update on what's new with RTL signoff.


    ...
    by Published on 06-19-2014 05:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11374-paras.jpg

    About a decade ago, semiconductor designs had just a few asynchronous clocks which were easily managed by designers through the process of manual design reviews. The situation today is completely different. An SoC can have hundreds of asynchronous clocks, driving different complex functions, spread across various IPs, supplied by different vendors. It’s just not possible to analyze the interaction of all these asynchronous clocks manually, and even the traditional tools are not sufficient. Tools need special intelligence to recognize the synchronized and unsynchronized crossings between various asynchronous clocks to identify design ...
    Published on 05-19-2014 04:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11073-atrenta-%40-dac-2014.jpg

    Last year at DAC, we launched the RTL Signoff platform and our customers responded enthusiastically. We even had a few other EDA companies follow our lead. So what have we been up to since then?

    Visit us at DAC this June and learn how we have expanded our industry leading RTL Signoff solutions to handle the next set of challenges in SoC design. Building on the success of our IP Signoff solution, we now offer a unique solution for SoC Signoff. This includes performance and capacity for billion+ gate designs through intelligent abstraction of models. A growing number of SoC design teams have standardized on our solutions and realized significant productivity gains.

    ...
    by Published on 04-30-2014 08:05 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/10879-gopro-hero-3-camera-front.jpg

    DAC is just 33 days away and who wouldn't want a cool GoPro camera to play with? Your manager will certainly want you to first check out what's new at DAC if your job involves getting to RTL signoff on time and within budget. The creative folks at Atrenta have figured out how to attract us with the offer of winning a GoPro camera, however you at least have to attend a product session in their suites to ...
    Published on 04-28-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/10848-atrenta-edps-2014.jpg

    First, I wish there were more conferences/workshops like this. This is much more about sharing ideas and brainstorming than the stark commercialism of DAC. I presented Atrenta’s role in enabling 3rd-party IP qualification for the TSMC soft IP library.

    My presentation slides are located here:

    http://www.eda.org/edps/Papers/5-3%2...d%20Murphy.pdf ...
    by Published on 04-12-2014 05:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/10706-methodology.jpg

    The SoC designs of today are much more complex than ever in terms of number of clocks, IPs, levels of hierarchies, several modes of operations, different types of validations and checks for growing number of constraints at various stages in the design flow. As a semiconductor design evolves through several stages from RTL to layout, the constraints may change. A consistency check on the changing constraints is desired to ascertain the intent to move in the right direction. Again there may be missing constraints ...
    by Published on 03-27-2014 09:01 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/10582-social-media-atrenta.jpg

    Atrenta is well-known for their SpyGlass software that enables SoC engineers to run early design analysis on RTL code and create a hardware virtual prototype for analysis prior to implementation. Visiting their website you quickly see that social media plays an important role in connecting with engineers as links for Facebook, Twitter, LinkedIn and RSS Feed are placed in the header.



    Let's take a closer look at each of these social media channels.
    ...
    by Published on 03-12-2014 08:15 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/10414-siddharth.jpg

    If we look at the past, most of the EDA tools in the semiconductor design space have originated from a designers’ need to do things faster. Regardless of whether it is design exploration, manual design, simulation, verification, optimization (Power Performance Area - PPA) and many other steps in the overall design flow. What matters most, is how fast is the overall design turnaround with all kinds of design closures such as functionality, timing, area and power. Many tools are lost in the middle of market dynamics ...

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