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  • Atrenta RSS Feed

    by Published on 03-27-2014 09:01 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/10582-social-media-atrenta.jpg

    Atrenta is well-known for their SpyGlass software that enables SoC engineers to run early design analysis on RTL code and create a hardware virtual prototype for analysis prior to implementation. Visiting their website you quickly see that social media plays an important role in connecting with engineers as links for Facebook, Twitter, LinkedIn and RSS Feed are placed in the header.



    Let's take a closer look at each of these social media channels.
    ...
    by Published on 03-12-2014 08:15 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/10414-siddharth.jpg

    If we look at the past, most of the EDA tools in the semiconductor design space have originated from a designers’ need to do things faster. Regardless of whether it is design exploration, manual design, simulation, verification, optimization (Power Performance Area - PPA) and many other steps in the overall design flow. What matters most, is how fast is the overall design turnaround with all kinds of design closures such as functionality, timing, area and power. Many tools are lost in the middle of market dynamics ...
    by Published on 02-21-2014 02:24 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/10258-bugscopeassertionsynthesis0.png

    As your SoC design can contain hundreds of IP blocks, how do you verify that all of the IP blocks will still work together correctly once assembled? Well, you could run lots of functional verification at the full-chip level and hope for the best in terms of code coverage and expected behavior. You could buy an expensive emulator to accelerate your verification process. You could try an Assertion-Based Verification (ABV) methodology and learn to manually write assertions. Or, you could consider using a methodology for assertion reuse in SoC designs.

    Two years ago ...
    by Published on 01-28-2014 08:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta,
    4. TSMC
    content/attachments/9927-piyush_new.jpg


    Ever since I have seen Atrenta’s SpyGlass platform providing a comprehensive set of tools across the semiconductor design paradigm, I felt the need for a common set of standards to evolve for sign-off at RTL level. Last December, when I read an EE Times article of Piyush Sancheti, VP, Product Marketing at Atrenta, where he talks about a billion gate SoC design, shrinking market windows, and design cycles to the level of 3-6 months, I was looking for an opportunity to talk to him in a broader sense on how RTL level design paradigm ...
    by Published on 01-21-2014 08:20 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/9831-power-savings-flow.jpg

    SoC designers can code RTL, run logic synthesis, perform place and route, extract the interconnect, then simulate to measure power values. Though this approach is very accurate, it's also very late in the implementation flow to start thinking about how to actually optimize a design for the lowest power while meeting all of the other design requirements. Ideally, you would want a flow that starts with your RTL code at the design phase and then provides a method to estimate power and even provide feedback on how to best reduce power long before physical implementation even ...
    by Published on 01-21-2014 03:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/9823-clk_gating.jpg

    Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that consume about 2/3rd of total chip power. So what? In a simplistic manner, it’s very easy to visualize the solution as, “gate the clock on ...
    by Published on 12-17-2013 05:51 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta

    It is that time of year and once again Atrenta has produced a video wishing you all the best for the holiday season. They are so spread around the world it is not just Hanukkah and Christmas but the Asian Lunar New Year (end of January) and probably some more holidays I don't even know about. Last year there was a competition to name all ...
    by Published on 11-18-2013 01:20 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/9273-ajoy2.jpg

    Today at the Semisrael Expo 2013 (in Israel of course) Ajoy Bose gave a keynote on how design methodology will impact electronics. The big pictures is that microelectronics is driven by some major disruptive forces and, as a result, technology and industry are evolving dramatically, which creates a need for research and innovation and also new business opportunities.

    What are these disruptive ...
    by Published on 11-07-2013 04:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/9139-rules.jpg

    There is always a rush to converge a semiconductor design toward faster closure, amid increasing divergent trends of multiple IPs and high complexities of various functionalities on a single chip. Every design house struggles hard to evolve its customized design flows with several short paths patched up to fix issues, global or local, at each stage in the design flow. And that becomes severe at the final layout stage, acting like a point of no return and warns – fix what you can, here and now, otherwise you are bound to lose the market ...
    by Published on 10-23-2013 11:31 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/8952-atrcdc2.jpg

    One of the first blogs I wrote on SemiWiki was on clock domain crossing (CDC). I thought it was rather a specialized subject, a sort of minority interest. It turned out to be one of the most-read blogs I've written. Modern SoCs have lots of unrelated clocks, maybe hundreds, and so ensuring that signals going from one clock domain to another are correctly handled is not a minority interest at all, it is right in the mainstream. ...

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