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    by Published on 10-16-2014 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/12245-design-team-priorities.jpg

    Complex SoC project teams typically use a divide and conquer approach where specialized engineers work in separate domains, like front-end or back-end. The five major engineering tasks for IC design can be described as: RTL design, synthesis, floor planning, place and route, then finally design analysis.



    What if you could detect physical implementation bottlenecks earlier in the design ...
    by Published on 09-28-2014 08:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/12111-signoff_flow.jpg

    With the unprecedented increase in semiconductor design size and complexity design teams are required to accommodate multiple design constraints such as multiple power domains for low power design, multiple modes of operation, many clocks running, and third party IPs with different SDCs. As a result timing closure has become extremely complex and tricky. While false paths may ...
    by Published on 08-30-2014 05:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11952-nextopgenericassertionsynthesis.jpg

    In college many of us dreamed of starting up our own company by offering something new that has never been done before. Today I spoke by phone with Yunshan Zhu in Shanghai, and he has actually lived out this scenario by founding NextOp in 2006, then getting that company acquired by Atrenta in 2012. The new capability that NextOp created was something called assertion synthesis, and the product name is BugScope.


    ...
    by Published on 08-22-2014 03:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11881-samantak1.jpg

    In the semiconductor design industry, most of the designs are created and optimized at the RTL level, mainly through home grown scripts or manual methods. As there can be several iterations in optimizing the hierarchy for physical implementation, it’s too late to do the hierarchical optimizations after reaching the floor plan or layout stage at the netlist level. All design explorations and optimizations must be therefore done at the RTL stage. The problem ...
    by Published on 07-31-2014 12:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11714-bugscope.jpg

    The last graphics chip that I worked on at Intel was functionally simulated with only a tiny display size of 16x16 pixels, because that size allowed a complete regression test to be simulated overnight. Our team designed three major IP blocks: Display Processor, Graphics Processor and Bus Interface Unit. We wanted to also integrate an 80186 core, ...
    by Published on 07-05-2014 10:20 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11497-semico-research.jpg

    Blogger Pawan Fangaria wrote about Clock Domain Crossing (CDC) a few weeks ago, and so I followed up tonight and watched a webinar about CDC presented by Ravindra Aneja of Atrenta. An RTL design engineer would ultimately want a CDC verification tool that offers:

    • Fast throughput and thoroughness
    • Ability to debug and fix the source of CDC errors
    • Handle billions of gates and be considered a signoff tool

    ...
    by Published on 06-30-2014 05:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11455-piyush-sancheti.jpg

    In the early days of Customer Owned Tooling (COT) the signoff was done at the GDS II, or physical level. Today, however we see the trend of RTL signoff instead because of the EDA tools and methodology available. At DAC earlier this month I met with Piyush Sancheti of Atrenta to get an update on what's new with RTL signoff.


    ...
    by Published on 06-19-2014 05:30 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11374-paras.jpg

    About a decade ago, semiconductor designs had just a few asynchronous clocks which were easily managed by designers through the process of manual design reviews. The situation today is completely different. An SoC can have hundreds of asynchronous clocks, driving different complex functions, spread across various IPs, supplied by different vendors. It’s just not possible to analyze the interaction of all these asynchronous clocks manually, and even the traditional tools are not sufficient. Tools need special intelligence to recognize the synchronized and unsynchronized crossings between various asynchronous clocks to identify design ...
    Published on 05-19-2014 04:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/11073-atrenta-%40-dac-2014.jpg

    Last year at DAC, we launched the RTL Signoff platform and our customers responded enthusiastically. We even had a few other EDA companies follow our lead. So what have we been up to since then?

    Visit us at DAC this June and learn how we have expanded our industry leading RTL Signoff solutions to handle the next set of challenges in SoC design. Building on the success of our IP Signoff solution, we now offer a unique solution for SoC Signoff. This includes performance and capacity for billion+ gate designs through intelligent abstraction of models. A growing number of SoC design teams have standardized on our solutions and realized significant productivity gains.

    ...
    by Published on 04-30-2014 08:05 AM
    1. Categories:
    2. Semiconductor Design,
    3. Atrenta
    content/attachments/10879-gopro-hero-3-camera-front.jpg

    DAC is just 33 days away and who wouldn't want a cool GoPro camera to play with? Your manager will certainly want you to first check out what's new at DAC if your job involves getting to RTL signoff on time and within budget. The creative folks at Atrenta have figured out how to attract us with the offer of winning a GoPro camera, however you at least have to attend a product session in their suites to ...

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