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    Missed #50DAC? See Aldec Verification Sessions Online 

    by
    Daniel Nenni
    Published on 06-12-2013 10:00 PM
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    Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs. With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community.

    ...
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    Advanced Verification - HW/SW Emulation - SoC/ASIC Prototyping 

    by
    Daniel Nenni
    Published on 05-29-2013 06:00 PM
    Article Preview

    Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs. With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community. Make ...
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    The never-ending quest to kill metastability 

    by
    Don Dingee
    Published on 05-28-2013 02:00 PM
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    The difficulty of an engineering problem can be gauged by two things:
    1) The number of attempts to generate a solution.
    2) The degree of hyperbole used to describe the effectiveness of the latest solution.

    The problem many folks in the EDA industry are after right now is clock domain crossings (CDCs) and the resulting metastability of designs. ...
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    It’s all in the details of FPGA requirements management 

    by
    Don Dingee
    Published on 05-23-2013 06:30 PM
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    Word association: if I said “requirements management”, you'd probably say IBM Rational “DOORS,” or maybe Serena or Polarion if you come from the IT world. But what if the requirements you need to manage are for an FPGA or ASIC, with HDL and testbench code and waveform files and more details backing verification, and compliance to safety-critical standards is needed?

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    A random walk down OS-VVM 

    by
    Don Dingee
    Published on 05-13-2013 09:14 AM
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    Unlike one prevailing theory of financial markets, digital designs definitely don’t function or evolve randomly. But many engineers have bought into the theory that designs can be completely tested randomly. Certainly there is value to randomness, exercising all combinations of inputs, including unexpected ones a designer wouldn’t try but a test engineer without a priori bias would.

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    Prototyping Over 100 Million ASIC Gates Capacity 

    by
    daniel_payne
    Published on 05-10-2013 10:42 AM
    1. Categories:
    2. EDA
    content/attachments/7190-hes7_logicboard_socessentials-small.jpg

    Most SoCs today are being prototyped in FPGA hardware before committing to costly IC fabrication. You could just design and build your own FPGA prototyping system, or instead choose something off the shelf and then concentrate on your core competence of SoC design.

    Thanks to the FPGA vendors like Xilinx we now have FGPA prototyping platforms that can reach over 100 million ASIC gates in capacity at a reasonable cost. Aldec has created ...
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    Wireless Algorithm Validation from System to RTL to Test 

    by
    Daniel Nenni
    Published on 05-07-2013 06:05 PM
    Article Preview

    This year's #50DAC will be chock-full of technical content because that is what attracts the masses of semiconductor professionals, like moths to a flame, or like me to a Fry's Electronics store. Interesting note, I went to high school with Randy Fry. His Dad started the Fry's supermarket chain which he sold then he went into electronics. That's why Fry's Electronics has a similar layout/business model as a grocery store.

    Agilent Technologies and Aldec ...
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