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  • Aldec RSS Feed

    by Published on 08-16-2014 11:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/11838-aldec-uvm-toolbox-uvm-graph.jpg

    One of the biggest endearing qualities of a debug environment for any type of coding is availability of multiple ways to accomplish a task. Whether the preference is keyboard shortcuts, mouse left-click drill-down and right-click pull-down menus, source code view, ...
    by Published on 07-30-2014 10:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. FPGA,
    4. Aldec
    content/attachments/11705-silly-crosswalk-norway.jpg

    Go ahead – type “open source” into the SemiWiki search box. Lots of recent articles on the IoT, not so many on EDA tools. Change takes a while. It has only been about five years since the Big Three plus Aldec sat down at the same table to work on UVM. Since then, ...
    by Published on 06-26-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. FPGA,
    4. Aldec
    content/attachments/11434-aldec-do-254cts-daughterboard.jpg

    Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot less certain and a lot more time consuming. ...
    by Published on 06-17-2014 07:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/11371-alint.jpg

    Tools, tools, tools. Designs are rapidly changing, JESD204b, Hybrid Memory cube and all other Gigabit serialization schemes are here to stay. RIP DDR. This means board level simulations with respect to firmware (FPGA) are going to be more challenging than ever. Why? you ask, especially if the board layout is simpler? True, but the data pipes are faster and wider, FPGAs denser, causing the board to do more in the same space. What tools ...
    Published on 05-02-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/10907-aldec-dac-banner.gif

    Dr. Stanley Hyduke founded Aldec in 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Today, Aldec EDA tools are used to design, simulate and verify FPGA, ASIC, SoC and embedded system designs. There are over 35,000 users of Aldec ...
    by Published on 04-22-2014 11:52 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/10804-design-files.jpg

    Learning an HDL language or an HDL simulator are two different things, so I wanted to see what was available for learning a vendor-specific HDL simulator. I've already taught Verilog as an instructor using both ModelSim and Active-HDL simulators, however we only used a handful of commands in the class and labs in order to focus on the language. I found out that an engineer at Aldec created a three part webinar on learning their HDL simulator, Active-HDL, so I watched part one, a 65 minutes video. The basic idea was to cover several key simulator concepts:

    ...
    by Published on 04-22-2014 06:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/10801-aldec-spectracer.jpg

    “Failure to plan is planning to fail.” If that is true – and it has been quoted verbatim or slightly modified so many times throughout modern history, there has to be some truth – why does most of the engineering community seem to detest planning so much?

    Engineering planning doesn’t mean whipping out a block diagram or pseudo code, then off to the implementation races – that worked in the old embedded days, and may still work in Makerville, with relatively small projects and few interfacing requirements. For bigger, sometimes safety-critical projects and the system-of-systems with ...
    by Published on 03-19-2014 10:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. FPGA,
    4. Aldec,
    5. Xilinx
    content/attachments/10493-a1.jpg

    I am convinced after studying out the matter, that Aldec is one of the leaders in DO254 certification. As you listen and read the news as I do about flight MA-370, you keep theorizing and wondering. This is a good time to introduce the reader to the seriousness of flight worthy electronics and the arduous process to achieve certification. First and foremost I recommend if your company is serious about designing airborne electronics that you attend ...
    by Published on 03-11-2014 06:30 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/10407-uvm-graph-window.jpg

    Most programmers can read a code snippet and spot errors, given enough hours in the day, sufficient caffeine, and the right lens prescription. As lines of code run rampant, with more unfamiliar third-party code in the mix, interprocedural and data flow issues become more important – and harder to spot.

    Verification IP particularly resembles that third-party code remark: vendors supplying UVM ...
    by Published on 02-28-2014 01:30 PM
    1. Categories:
    2. Semiconductor Design,
    3. FPGA,
    4. Aldec,
    5. Xilinx
    content/attachments/10319-iphone-5s-release.jpg

    Back in the days where computing was dominated by a few big (and now mostly dearly departed) names, there was a saying: “Nobody ever got fired for buying IBM.” The relative safety of immediate brand recognition, especially among non-technical upper management, dissuaded many users from recommending or even seeking out other options. Non-justification was just easier.

    Technology changed, but people haven’t. Many users still make tech buying decisions based on risk-aversion ...

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