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    by Published on 11-29-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/12652-aldec-riviera-pro-2014.10-verification-plan.jpg

    Coverage is an important yet elusive metric for design verification. It often seems 90% of coverage comes with 10% of the effort, and getting the final 10% covered takes the remaining 90% of a project. Usually, it takes another tool or methodology to get at the 10% the first tool missed. With 100% closure difficult, most teams inspect what hasn’t been covered ...
    by Published on 10-25-2014 03:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/12345-hardware-dependent-software-hds-.jpg

    Why is software for modern SoCs so blasted expensive to develop? One reason is more software is being developed at the kernel layer – hardware dependent software, or HdS. Application software often assumes the underlying hardware, operating system, communication stacks, and device drivers are stable. For HdS, this flawed assumption of stability can eat a project alive. ...
    by Published on 09-26-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. FPGA,
    4. Aldec
    content/attachments/12126-2-ff-synchronizer.jpg

    Multiple clock domains in FPGAs have simplified some aspects of designs, allowing effective partitioning of logic. As FPGA architectures get more flexible in how clock domains, regions, or networks are available, the probability of signals crossing clock domains has gone way up. ...
    by Published on 08-17-2014 12:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/11838-aldec-uvm-toolbox-uvm-graph.jpg

    One of the biggest endearing qualities of a debug environment for any type of coding is availability of multiple ways to accomplish a task. Whether the preference is keyboard shortcuts, mouse left-click drill-down and right-click pull-down menus, source code view, ...
    by Published on 07-30-2014 11:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. FPGA,
    4. Aldec
    content/attachments/11705-silly-crosswalk-norway.jpg

    Go ahead – type “open source” into the SemiWiki search box. Lots of recent articles on the IoT, not so many on EDA tools. Change takes a while. It has only been about five years since the Big Three plus Aldec sat down at the same table to work on UVM. Since then, ...
    by Published on 06-26-2014 07:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. FPGA,
    4. Aldec
    content/attachments/11434-aldec-do-254cts-daughterboard.jpg

    Vector blasting hardware is as old as digital test methodology itself. In the days of relatively simple combinational and finite state machine logic, a set of vectors aimed broadside at inputs could shake loose most faults with observable outputs. With FPGAs, creating an effective set of artificial test vectors has become a lot less certain and a lot more time consuming. ...
    by Published on 06-17-2014 08:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/11371-alint.jpg

    Tools, tools, tools. Designs are rapidly changing, JESD204b, Hybrid Memory cube and all other Gigabit serialization schemes are here to stay. RIP DDR. This means board level simulations with respect to firmware (FPGA) are going to be more challenging than ever. Why? you ask, especially if the board layout is simpler? True, but the data pipes are faster and wider, FPGAs denser, causing the board to do more in the same space. What tools ...
    Published on 05-02-2014 07:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/10907-aldec-dac-banner.gif

    Dr. Stanley Hyduke founded Aldec in 1984 and their first product was delivered in 1985, named SUSIE (Standard Universal Simulator for Improved Engineering), a gate-level, DOS-based simulator. The SUSIE simulator was priced lower than other EDA vendor tools from the big three: Daisy, Mentor and Valid (aka DMV). Today, Aldec EDA tools are used to design, simulate and verify FPGA, ASIC, SoC and embedded system designs. There are over 35,000 users of Aldec ...
    by Published on 04-23-2014 12:52 AM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/10804-design-files.jpg

    Learning an HDL language or an HDL simulator are two different things, so I wanted to see what was available for learning a vendor-specific HDL simulator. I've already taught Verilog as an instructor using both ModelSim and Active-HDL simulators, however we only used a handful of commands in the class and labs in order to focus on the language. I found out that an engineer at Aldec created a three part webinar on learning their HDL simulator, Active-HDL, so I watched part one, a 65 minutes video. The basic idea was to cover several key simulator concepts:

    ...
    by Published on 04-22-2014 07:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Aldec
    content/attachments/10801-aldec-spectracer.jpg

    “Failure to plan is planning to fail.” If that is true – and it has been quoted verbatim or slightly modified so many times throughout modern history, there has to be some truth – why does most of the engineering community seem to detest planning so much?

    Engineering planning doesn’t mean whipping out a block diagram or pseudo code, then off to the implementation races – that worked in the old embedded days, and may still work in Makerville, with relatively small projects and few interfacing requirements. For bigger, sometimes safety-critical projects and the system-of-systems with ...

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