You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • Synopsys RSS Feed

    by Published on 07-16-2014 01:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/11577-avago-synopsys.jpg

    Test engineers are often the unsung heroes in the semiconductor world, because they have the tough job of deciding if each IC is good or bad, while taking the least amount of time on a tester and ensuring that the tests are actually finding and uncovering all manufacturing and process variation defects. Simple stuck-at fault models are no longer sufficient to catch all of the actual defects, so to achieve the highest quality and lowest Defective Parts Per Million (DPPM) new Transition Delay (TD) patterns are being used. Extending TD testing with Slack-Based Transition Delay (SBTD) testing is a new approach for even higher defect coverage. A recent webinar presented by Synopsys and Avago focused on this test topic.

    ...
    by Published on 06-30-2014 04:02 PM
    1. Categories:
    2. Semiconductor Design,
    3. Runtime Design Automation,
    4. Synopsys
    content/attachments/11459-sfv2.jpg

    Synopsys announced verification compiler a couple of months ago and dropped hints about their static and formal verification. They haven't announced anything much for a couple of years and it turns out that the reason was that they decided that the technology that they had, some internally developed and some acquired, wasn't a good basis for going forward and they needed to rebuild everything from ...
    by Published on 06-22-2014 01:01 AM
    1. Categories:
    2. Semiconductor IP,
    3. Synopsys
    content/attachments/11395-voicecontrol.jpg

    The ARC EM family is the low-power, embedded and low footprint processor part of the larger ARC processor. To target the ultra low-power markets like wearable and IoT, Synopsys has added DSP capabilities to EM5D and EM7D. To be specific, these cores are optimized for ultra low-power control and DSP, thanks to:

    • Energy-efficient 3-stage RISC pipeline
    • Unified single cycle 32x32 MUL/MAC unit
    • Energy-efficient signal processing
    ...
    by Published on 06-12-2014 07:53 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/11334-synopsys-acquisitions-product-launch.jpg

    Synopsys has been extremely active, during the last 10 years, not only launching new IP products every year, but also running an ambitious acquisition strategy, with no less than 8 acquisitions. Cascade acquisition bring PCI Express (controller only), when Accelerant bring SerDes (the earth of any PHY IP). The MIPS/Chipidea acquisition, made opportunistically during the 2009 depression, has allowed Synopsys to add Analog IP (ADC, DAC, Codec…) to the port-folio, as well as a large analog-skilled team. The 18X ...
    by Published on 06-05-2014 09:36 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/11260-galaxy-design-platform.jpg

    This is a new brick that Synopsys brings to build FD-SOI credibility. We have talked at Semiwiki about FD-SOI technology developed by the LETI and STM, and recently endorsed by Samsung Foundry, offering a more than credible second source to STM. And we have said that the FD-SOI introduction will need to be supported by EDA and IP vendors to be successful. The announcement that Synopsys design flow support of 28-nm FD-SOI ...
    by Published on 06-04-2014 12:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/11249-thermal-grease.jpg

    How much power does a system consume? The simplistic path to power estimation for a system used to be tossing a few metrics – standby, typical, worst case, with figures pulled from a datasheet, simulation, or physical measurement – into a spreadsheet. After filling the remaining holes with SWAG (scientific wild-ass guesses), and summing things up, there was a bottom line.

    But, that bottom line on power was imprecise at best. Designers were usually after worst case, because it determined system cost. ...
    by Published on 06-02-2014 02:15 PM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/11244-image.jpg

    Synopsys hosted an AMS Luncheon panel today at DAC in the Westin Hotel and invited four customers to talk about their actual design challenges and experiences. I've typed up my notes from this event.



    ...
    by Published on 05-28-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/11152-fpga-synthesis-run-time.jpg

    We’ve all heard this claim: “Our FPGA synthesis tool produces better quality of results (QoR).” If you’re just hoping for a tool to do that automagically, you’re probably doing it wrong. Getting better QoR depends on understanding what an FPGA synthesis tool is capable of, and how to leverage what it tells you. ...
    Published on 05-14-2014 09:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    Article Preview

    Accelerating Innovation—that has been at the heart of Synopsys’ commitment to its customers for more than 25 years. As a leader in EDA and semiconductor IP, Synopsys’ software, IP and services help engineers address their design, verification, system and manufacturing challenges and accelerate their innovations. Since 1986, engineers around the world have used Synopsys technology to design and create billions of chips and systems. What will you design next? Visit ...
    by Published on 05-08-2014 10:50 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/10964-micron-synopsys.jpg

    IDM companies like Micron use SPICE circuit simulators during the design phase in order to predict timing, currents and power on their custom IC chip designs at the transistor level. A senior memory design engineer at Micron named Raed Sabbah talked today at a webinar about how the embedded solutions group uses the FineSim circuit simulator from Synopsys during the design and verification flow. My background includes DRAM design, so I felt at home listening to Raed.


    Chip photo of 16nm NAND for 16GB storage
    ...

    Page 1 of 17 12311 ... LastLast