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  • Synopsys RSS Feed

    by Published on 03-31-2014 02:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/10615-dlcar.jpg

    Sebastian Thrun gave a fascinating keynote at SNUG last week. It didn't have that much to do with IC design but he discussed 3 projects that he had been involved with. Anyone would be happy to have just one of these projects on their resume but he has all these (and more).

    The first is the Google self-driving car. This project actually started 10 years ago in ...
    by Published on 03-30-2014 09:34 AM
    1. Categories:
    2. Semiconductor IP,
    3. Synopsys
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    In fact, this assertion is provocative, as the DDR4 protocol standard has just been released by JEDEC… after 10 years discussion around the protocol features. Yes, the first discussions about DDR4 have started ten years ago! Will DDR4 be used in the industry? The answer is certainly yes, and DDR4 will most probably be used for years. But memory controllers experts, like Graham Allan, Sr Marketing Manager at Synopsys (and active JEDEC ...
    by Published on 03-26-2014 11:00 AM
    1. Categories:
    2. Semiconductor IP,
    3. Synopsys
    content/attachments/10567-better-software-faster-best-practices-virtual-prototyping.jpg

    Shipping a product with complete software support at official release is a lot more difficult than it sounds. Inevitably, there is less than enough hardware to go around, and what little there is has to fill the needs of hardware designers, test and certification engineers, software development teams, systems integration teams, sales and channel training organizations, marketing communications and event managers, and often beta customers. ...
    by Published on 03-25-2014 02:04 PM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
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    I have been at SNUG for the last couple of days. The big announcement is IC Compiler II. It was a big part of Aart's keynote and Monday lunch featured all the lead customers talking about their experience with the tool.

    The big motivation for IC Compiler II was to create a fully multi-threaded physical design tool that will scale well on multi-core processors and large server farms. The original IC Compiler, ...
    by Published on 03-25-2014 08:02 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
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    Digital verification engineers on SoC designs have adopted many techniques to help ensure first silicon success: using compiled simulators, constrained random test, simulation farms, SystemVerilog methodology, and self-checking testbenches. AMS verification has tended to be ad-hoc or sharply divided into separate analog verification and digital verification realms.

    Synopsys has decided to start applying some of these digital verification ...
    by Published on 03-24-2014 08:05 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/10426-icc-ii-graphic_press2.jpg

    EDA start-up companies often have the advantage over established vendors by being able to start from scratch, instead of having to maintain some legacy code that no longer is competitive. But what happens when the established vendor decides to rewrite their IC implementation tools from scratch? In this case it's good news, because Synopsys has just announced a rewrite of their popular IC Compiler and have dubbed it IC Compiler II. I talked with Saleem Haider of Synopsys earlier this month by phone to get briefed about it.


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    by Published on 03-04-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/10326-vc2.jpg

    Integration is often an underrated attribute of good tools, compared to raw performance and technology. But these days integration is differentiation (try telling that to your calculus teacher). Today at DVCon Synopsys announced Verification Compiler which integrates pretty much all of Synopsys's verification technologies (including the technology acquired in the SpringSoft acquisition) into a single tool. Verification Compiler is a complete portfolio of integrated, next-generation verification ...
    by Published on 03-04-2014 02:33 AM
    1. Categories:
    2. Semiconductor IP,
    3. Synopsys
    content/attachments/10363-12g-ethernet-spotlight.jpg

    I have often written in Semiwiki about high speed PHY IP supporting Interface protocols (see for example this blog), the SoC cornerstone, almost as crucial as CPU, GPU or SDRAM Memory Controller. When you architect a SoC, you first select CPU(s) and/or GPU(s) to support the system basic functionality (Processor for Mobile application, Networking, Set-Top-Box etc.), then you define the various protocols to be supported by this SoC to interface with the functional ...
    by Published on 02-28-2014 10:17 AM
    1. Categories:
    2. Semiconductor Design,
    3. Synopsys
    content/attachments/10313-zebu1.jpg

    Since Synopsys acquired Eve over a year ago, they haven't announced anything new in the ZeBu product line. Emulators are not like software where you expect incremental releases a couple of times per year, each new "release" is a complete re-design using new hardware fabric in a new process technology. Earlier this week Synopsys announced Zebu Server-3, currently the industry's fastest emulation system (to be fair, whenever ...
    by Published on 02-20-2014 03:00 PM
    1. Categories:
    2. Semiconductor IP,
    3. Synopsys
    content/attachments/10248-ip-block-growth-socs.jpg

    By now, you’ve probably seen the news on Synopsys acquiring Coverity, and a few thoughts from our own Paul McLellan and Daniel Payne in commentary, who I respect deeply – and I’m guessing there are many like them out there in the EDA community scratching their heads a little or a lot at this. I'm not from corporate, but I am here to help.

    Coverity and other purveyors of C/C++ static code analysis tools come from ...

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