is part of the Design Closure Methodology group at LSI
and he recently talked about his ASIC handoff experience in a webinar
. Harish works with logic and physical synthesis, timing constraints, RTL analysis and formal verification.
One challenge with ASIC handoff has been getting through design closure with the fewest iterations so that the physical design still meets timing, power and area budgets. To reduce these iterations Synopsys
engineered the Design Compiler Graphical
tool to offer an approach with a better starting point for faster physical implementation. LSI has successfully used Design Compiler Graphical in