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    Carl Icahn Blinks in Bid for Mentor Graphics 

    by
    daniel_payne
    Published on 05-02-2012 01:42 PM
    1. Categories:
    2. EDA,
    3. Mentor Graphics
    Article Preview

    One year ago activist investor Carl Icahn started a hostile takeover bid for Mentor Graphics and was able to offer up three new board members, however yesterday we read that Mentor Graphics will:


    • Have their annual shareholder meeting on May 30th
    • Two of Icahn's board members are not on the roster for renewal
    • Mr. Icahn has no new board members to offer
    ...
    Read More Read More 10 Comments

    IC Reliability and Prevention During Design with EDA Tools 

    by
    daniel_payne
    Published on 04-27-2012 03:04 PM
    1. Categories:
    2. EDA,
    3. Mentor Graphics
    content/attachments/3540-eos.jpg.html

    IC device physics uncovers limits to reliable operation, so IC designers are learning to first identify and then fix reliability issues prior to tape-out. Here' s a list of reliability issues to keep you awake at night:
    ...
    Read More Read More 9 Comments

    Mentor's New Emulator 

    by
    Paul McLellan
    Published on 04-25-2012 06:00 AM
    content/attachments/3486-ment1.jpg.html

    Mentor announced the latest version of their Veloce emulator at the Globalpress briefing in Santa Cruz. The announcement is in two parts. The first is that they have designed a new custom chip with twice the performance and twice the capacity. It supports up to two billion gate designs and many software engineers. Surprisingly the chip is ...
    Read More Read More

    Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE) 

    by
    daniel_payne
    Published on 04-18-2012 10:38 AM
    1. Categories:
    2. EDA,
    3. Mentor Graphics
    Article Preview

    Smaller IC nodes bring new challenges to the art of IC layout for AMS designs, like Layout Dependent Effects (LDE). If your custom IC design flow looks like the diagram below then you're in for many time-consuming iterations because where you place each transistor will impact the actual Vt and Idsat values, which are now a function of proximity to a well:


    Source: EE Times, Mentor Graphics

    Analog designs are most sensitive to variations in Vt and current levels, especially for circuit designs that need precise matching.

    Engineers at Freescale Semiconductor ...
    Read More Read More 6 Comments

    Doing what others don't do 

    by
    Paul McLellan
    Published on 04-12-2012 12:56 PM
    content/attachments/3361-u2u.jpg.html

    Wally Rhines' keynote at U2U, the Mentor users’ group meeting, was about Mentor’s strategy of focusing on what other people don’t do. This is partially a defensive approach, since Mentor has never had the financial firepower to have the luxury of focusing all their development on sustaining their products and then make acquisitions of startups to get new technology. Even when they have ...
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    U2U Mentor Users' Group 

    by
    Paul McLellan
    Published on 04-04-2012 08:58 AM
    content/attachments/3278-wally.jpg.html

    Mentor's U2U user group meeting in Santa Clara is next week on April 12th at the Santa Clara Marriott. For those of you on the east coast the Waltham U2U is on May 16th, and for Europeans the Munich U2U will be on October 25th. Registration is open for both Santa Clara and Waltham, and there is a call for papers for Munich.

    The day starts ...
    Read More Read More

    Conquering the Big Data Challenges 

    Published on 04-02-2012 02:38 PM  Number of Views: 1279 
    1. Categories:
    2. EDA,
    3. Mentor Graphics
    content/attachments/3256-fig1-flat.jpg.html

    Extrapolating the trends from last 20 years to the next ten suggests that we will be implementing a trillion transistors or more by 2020. At 20nm, with the chip sizes touching billions of transistors, the age old problem of how to implement a design in the most efficient manner remains unanswered.



    ...
    Read More Read More 2 Comments

    3D-IC Testing – A 3D perspective to SoC 

    by
    Pawan Fangaria
    Published on 03-21-2012 07:30 AM
    content/attachments/3194-image1.jpg.html

    In my last article I talked about the physical design aspect of 3D-IC. Now looking at its verification aspect, it spans through a wide spectrum of test at hardware as well as software level. The verification challenge goes much beyond that of a SoC which is at a single plane. Even a typical SoC that comprises of a processor core, memory controller, GPU, IP block and peripheral units is very difficult to test as a whole ...
    Read More Read More 8 Comments

    Double Patterning and Then The End of Lithography 

    by
    Paul McLellan
    Published on 03-15-2012 06:00 AM
    content/attachments/3157-dpat.jpg.html

    I went to a couple more sessions at the Common Platform Technology Forum today, on 20nm double patterning and whatever will we do at 14nm. Basically, this is the end of planar transistors and the end of optical lithography. One session was by IBM scientists about process and one by Michael White of Mentor about double patterning. These two subjects turn out to be very related.

    ...
    Read More Read More 10 Comments

    Seminar on IC Yield Optimization at DATE on March 14th 

    by
    daniel_payne
    Published on 02-22-2012 01:59 PM
    1. Categories:
    2. Mentor Graphics,
    3. Global Foundries
    content/attachments/2918-fig1.jpg.html

    My first chip design at Intel was a DRAM and we had a 5% yield problem caused by electromigration issues, yes, you can have EM issues even with 6um NMOS technology. We had lots of questions but precious few answers on how to pinpoint and eliminate the source of yield loss. Fortunately, with the next generation of DRAM quickly introduced this yield issue was less urgent.
    ...
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