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    by Published on 06-19-2012 02:29 PM  Number of Views: 1298 
    content/attachments/4094-eagle1.jpg

    Foreign students earn roughly two-thirds of the total engineering Ph.D.s earned in the U.S., yet there is no policy to allow, let alone encourage, them to stay in the U.S. after graduation. I was aware of this problem 14 years ago when I started working in EDA, but haven't paid much attention since then.

    So, I scoured the congressional websites to learn what our leaders have ...
    by Published on 06-17-2011 03:46 PM  Number of Views: 1389 
    1. Categories:
    2. EDA,
    3. TSMC_Foundry
    content/attachments/1330-powertrim.jpg

    Intro
    Neal Carney, VP of Marketing at Tela Innovations provided me an update at DAC last week. Their company partnered with TSMC to reduce leakage in IC designs by biasing the gate lengths on your paths that are non-critical to timing.

    Notes


    Why do this?
    - Reduce leakage
    - Increase gate lengths on paths with slack
    - Recharacterize cells ...
    by Published on 06-17-2011 03:37 PM  Number of Views: 1584 
    1. Categories:
    2. EDA,
    3. Cadence

    Intro
    I remember when Celestry was acquired by Cadence because that gave them a hierarchical Fast SPICE simulator to compete with HSIM. In 2007 part of Celestry spun out from Cadence and became Proplus, which now offers a SPICE simulator called NanoDesigner.

    Notes
    Proplus – US company, founded ...
    by Published on 06-17-2011 03:23 PM  Number of Views: 2724 
    1. Categories:
    2. EDA
    content/attachments/1327-dac-edxact.jpg

    Intro
    Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.

    Daniel Borgraeve (on right)

    Notes
    Edxact
    - Started seven years ago
    - Fifteen people in the company
    - Based in France
    - Jivaro: RLCK reduction ...
    by Published on 06-17-2011 02:20 PM  Number of Views: 2338 
    1. Categories:
    2. EDA
    content/attachments/1320-dac-micro-magic.jpg

    Intro
    Micro Magic was the only company at DAC that showed an IC layout editor with 1 Trillion transistors loaded in it, wow.


    Karen Mangum

    Notes
    I chatted with Katherine Hays, a 12 year veteran of Micro Magic about what was new at DAC this year.

    Max-3D – Can handle stacked wafers with TSV
    - Gary Smith’s list of must-see for 3D
    - New for 2011: 3D ...
    by Published on 06-14-2011 01:01 PM  Number of Views: 1653 
    1. Categories:
    2. EDA
    content/attachments/1293-extreme-da-flow.jpg

    Intro
    Over the lunch hour on Tuesday at DAC I met with Emre Tuncer, VP – Product Engineering & Applications and heard about extraction and timing analysis.

    Notes




    GoldX – parasitic extractor. Fast extractor, recently announced, all new technology, early customer adoption. One customer deploying it in 40nm, soon to be 28nm.
    - Sold stand alone. ...
    by Published on 06-14-2011 11:03 AM  Number of Views: 999 
    1. Categories:
    2. EDA
    content/attachments/1288-technology1.jpg

    Intro
    It's all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what's new for 2011.




    Notes

    What’s New in 2011 at Blue Pearl Software

    New designer experience, ease of use. Brand new GUI.

    Work with RTL to synthesis tools to get best timing in your layout.

    GUI – windows 7 and Linux, same look and feel.
    - All new in 2011
    - Inline help

    Blue Pearl Analyze – Linting, race checks, ...