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    by Published on 03-21-2014 03:18 PM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor IP,
    4. Events

    DAC is in the first week of June in San Francisco as I'm sure you already know if you are reading this. Historically DAC has focused on electronic design automation (EDA) and embedded software and systems (ESS). This year there are three new areas: automotive, Intellectual Property (IP) and security.

    Ever increasing feature content enabled by electronics and software and the associated complexity ...
    by Published on 03-19-2014 11:00 AM
    1. Categories:
    2. Semiconductor Design,
    3. Semiconductor Manufacturers

    As you can't have failed to notice by now, 28nm is the last process node that does not require double patterning. At 20nm and below, at least some layers require double patterning. The tightest spacing is typically not the transistors but the local interconnect and, sometimes, metal 1.

    In the litho world they call double patterning LELE. This stands for litho-etch-litho-etch which describes the steps taken. Using the first ...
    by Published on 03-15-2014 08:00 PM
    1. Categories:
    2. FPGA

    For the connected, in the instant knowledge, information world we live in, the missing Malaysia Airlines Flight 370 is most humbling. Let us be reminded as we look for details, and theorize… that someone’s Father, Mother, Brother, Sister, Son, Daughter, Friend are missing. Just terrible but the Miller’s continue to pray and hope for that miracle.

    What have we learned from a technology standpoint? Me, being a RADAR/EW fella, it amazes ...
    by Published on 03-10-2014 01:24 PM
    1. Categories:
    2. Events

    I wrote recently about the EDAC mixer in Mountain View. Due to college basketball there won't be one in March, the next one will be in April. Details later in the month.

    The EDA Consortium (EDAC) is seeking nominations for the Board of Directors for the two-year term beginning May 29, 2014. Voting member companies are entitled to nominate their CEO, president or COO to serve on the consortium's ...
    by Published on 03-09-2014 06:34 PM
    1. Categories:
    2. Semiconductor Design

    I first started using WordPress in 2008 after having written my own Content Management System (CMS) to build and manage web sites. WordPress is the number one CMS in the world, is just 10 years old, and is used by over 70 million users. What got me thinking about WordPress and EDA software companies was a recent book by Scott Burken, The Year Without Pants: and the Future of Work. In the book Scott ...
    Published on 03-07-2014 06:00 AM
    1. Categories:
    2. Semiconductor Design

    Inside a today’s typical VLSI system, there are millions of electrical signals. They make the system perform what it is designed to do. Among those, the most important one is the clock signal. From an operational perspective, clock is the timekeeper of the electrical world inside the chip/system. From a structural perspective, clock generator is the heart of the chip; clock ...
    by Published on 03-04-2014 05:36 PM
    1. Categories:
    2. Semiconductor Design

    I started using internal EDA tools at Intel beginning in 1978 and have worked in the commercial EDA industry since 1986, so it was a delight to read a chapter about EDA in Nenni and McLellan's newest book: Fabless - The Transformation of the Semiconductor Industry. Starting in the 1970's the authors talk about EDA, Phase One and how painfully manual the whole process of designing an Integrated Circuit was. I'll never forget working at Intel at the time and performing manual Design Rule Checks (DRC) on an IC layout, when I stopped to ask my manager, "Hey, what about using a software program to automate this tedious task?"

    Published on 03-02-2014 09:00 AM
    1. Categories:
    2. Semiconductor Design

    In previous design generations interconnect could safely be modeled by extraction using just R and C values. Parasitics in interconnect are important because they can affect the operating frequency or phase error in circuits like VCO’s. The need to model parasitics properly in wires is just as applicable in PA’s, LNA’s and for clock lines, or any other place there ...
    by Published on 03-01-2014 03:19 PM
    1. Categories:
    2. Semiconductor Manufacturers

    Back in the 1990s in the middle of the 2G GSM era, cell-phone manufacturers would display a "triangle of difficulty" with a large base labeled radio, a middle smaller part labeled baseband and a little triangle on top labelled software. The idea was that the radio was incredibly difficult, then the baseband chip and there wasn't a lot of work on software since there wasn't that much in a phone of that era. But they would point out that that was then and now the triangle was inverted. ...
    by Published on 02-28-2014 06:31 AM
    1. Categories:
    2. Events

    Yesterday evening was EDAC's first mixer. I assume the first of a regular event. It was held in Mountain View in the old train station which is now the Savvy Cellar wine bar. I had a nice glass of rosé from Provence that reminded me of the years that I lived in the south of France. Some of the money we spent went to charity, to the Mountain View Educational Foundation (MVEF).

    To my surprise I discovered another ...

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