My first chip design at Intel was a DRAM and we had a 5% yield problem caused by electromigration issues, yes, you can have EM issues even with 6um NMOS technology. We had lots of questions but precious few answers on how to pinpoint and eliminate the source of yield loss. Fortunately, with the next generation of DRAM quickly introduced this yield issue was less urgent.
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Being an internationally recognized industry blogger (IRIB) does have its benefits, one of which is free invites to all of the cool industry conferences! The presentations are canned for the most part but you can learn a lot at the breaks and exhibits if you know the right questions to ask, which I certainly do.

The GSA Semiconductor Ecosystem Summit is an executive conference focused on three core components of the semiconductor business model - supply chain practices, technology evolution, and financial trends. Distinguished executives from leading semiconductor companies will address critical topics including collaboration in the mobile ecosystem, supply chain practices for sustainable partnerships, smart technology development, hardware/software ...

Stephen Crosher started up Moortec in the UK back in 2005 with the help of his former Zarlink co-workers and they set to work offering AMS design services and eventually created their own Analog IP like the temperature sensor shown below:

We spoke by phone last week about his start-up experience and how they approach AMS design.


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Last week GLOBALFOUNDRIES and Mentor Graphics presented at the Tech Design Forum on how they collaborated on a third generation DFM flow. When I reviewed the slides of the presentation it really struck me on how the old thinking in DRC (Design Rule Checking) of Pass/Fail for layout rules had been replaced with a score represented as a number between 0 and 1.





An example is shown above where an enclosure rule is described as:
The top Metal line has a Via with short overlap ...

Introduction
Mentor Graphics and GLOBALFOUNDRIES have been working together for several generations since the 65nm node on making IC designs yield higher. Michael Buehler-Garcia, director of Calibre Design Solutions Marketing at Mentor Graphics spoke with me by phone today to explain how they are working with GLOBALFOUNDRIES on a 3rd generation DFM (Design For Manufacturing) flow.

3rd party IP providers like ARM and Virage have been using this evolutionary ...

Dipesh Patel, VP Engineering, ARM Physical IP

Consumer demand for smart devices, short life cycles (SmartPhone, Tablets, Internet screens)

Processor speeds: 1GHz to 1.5GHz
SOC Memory: 600MHz to 1.2 GHz
How power efficient?
How is the layout density?

Standard Cells: multi-channel, multi-vt (4) libraries

Memory Compilers: single port, multi port, ROM
7 families to choose from

28nm libraries nominal VDD of 1.0V

Processor Optimization Package (POP)
- ...

Intro
The 28nm nodes is ready with foundry silicon, IP and EDA tools. Tuesday morning at the DAC breakfast I learned more about the 28nm eco-system.


Notes
Why 32/28nm
- Lower power, high integration requirements, mobile applications

What is Ready?
- IP is qualified (ARM, Memories, Foundation IP, SNPS IP, PDKs)
- August 2010 SNPS and GLOBALFOUNDRIES at 28nm
- June 2011 SNPS and ARM at 28nm (A15 core)
- June 2010 Samsung at 32nm with SNPS tools
- Common Platform – Lynx tool flow is ready, January 2011
- June 2011 GLOBALFOUNDRIES ready at 28nm
- Samsung qualifies 28nm
- Samsung at 35 tape outs at 32nm to date


Anna Hunter, VP Samsung
Technology Roadmap
- 32nm LP: ready, HKMG process
o SRAM at .149um*um, tiny size
o Good yield at 86%
o Matches SPICE results
- 28nm LP: ready
o Same HKMG as 32nm node
o Works with ARM IP and SNPS tool flow
- 28nm LPH: under development (low power, plus higher performance modules)
o Will be up to 50% faster (with more leakage, 2.3X)
o Same HKMG
o Added strain to silicon
o Shuttles starting now
- 20nm LPM: in development, PDK evaluation now. Ready by end of 2012.

Lynx – flow of SNPS tools and IP management, used by Samsung internally too

ARM CPU – 45nm >1GHz on Cortex A9
- 32/28nm >1.35GHz on Cortez A15
- 28nm LPH, >2.0GHz Cortex A15

IP Portfolio – High Speed, Memory, Mixed Signal
- ARM, SNPS<

Going from 45nm to 32nm more than 50% improvement in SRAM bit cell size

Turn key solutions from Samsung
- Design, Fab, Wafer Sort, Assembly, Final Test
- Working on TSV technology for higher integration on packaging

MPW – Run every quarter for 32nm and 28nm
- Will start 20nm in September

Fab sites – Korea( 20nm), Texas (40K wafers per month)

Jim Ballingall, VP Marketing at GLOBALFOUNDRIES
- AMD lead product used HKMG technology, quad core CPU with GPU integrated, 500GFlops, for notebooks
- Llano powered laptops later in June

Super Low Power – 28nm SLP (doesn’t use stressing), about 2.3GHz

High Performance Plus – 28nm HPP (uses stressing), about 3.1GHz
...

Introduction
Monday morning at DAC I attended the breakfast presentation from Magma, ARM and GLOBALFOUNDRIES. The 28nm node is ready for business using Magma tools and ARM libraries.

During breakfast I met Karim Arabi, Ph.D. from QualComm. He's a senior director of engineering in San Diego and wanted to learn more about the 28nm node and how Magma tools could be used in a flow.



Notes


Rod Metcalf – Magma, 28nm Reference Flow Development, using the Talus flow manager for the entire IC design flow. We ran a testcase to ensure silicon validation. ...

Although there has been always a strong relationship between Kilopass and Chartered Semiconductor, this relationship has been even enhanced after the acquisition of Chartered by GLOBALFOUNDRIES, allowing Kilopass’s customers to integrate NVM IP on advanced technology nodes, down to 40nm or even 28nm in the near future.







Before going more in detail into the NVM technology and type of IP available on GLOBALFOUNDRIES technologies, I would like to understand to which extent NVM is –and will be in the future- a strategic piece of a SoC design. To do so, let’s try to quickly build a forecast for IC, ASIC or ASSP, which will integrate at least one NVM IP. This NVM can be used for:

• Chip Identification (unique ID per IC)


• Trimming or calibration (usually for mixed signal IC)


• Coefficient storage (specific to Image sensor)


• Configuration


• ROM patching


• MCU code storage

We will look at the two major market segments where NVM is commonly used: Mobile Electronic Devices (Wireless handset and Media Tablet) and Consumer Electronics (Set-Top-Box and HDTV), simply because the applications from these two segments are generating huge production volumes. Using information from the very good article: “Reap the Benefits without the Cost: Mobile Handset Chips Utilize Antifuse NVM from Configuration to Code Storage” that you can find here (***), we have been able to evaluate the number of IC using NVM in a Smartphone, as well as in the more traditional feature phone and low cost handset. We have used the Wireless Handset 2010-2015 forecast built by IPnest to evaluate the number of systems, as well as some data from ABI research for the Media Tablet, so we have built the following table:Let me be precise and state that we had to make some approximation: the Automotive and Industrial segments ...