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Mentor Graphics
View from the top: Michael Buehler-Garcia

by
daniel_payne
Published on 05-15-2012 08:30 AM

Categories:

EDA,

Mentor Graphics

Yesterday I met with Michael Buehler-Garcia, Director of Marketing at Mentor Graphics for Calibre in Wilsonville, Oregon to get an update on what's coming up at DAC, the premier conference and trade show for our industry.

...

Read More
Carl Icahn Blinks in Bid for Mentor Graphics

by
daniel_payne
Published on 05-02-2012 01:42 PM

Categories:

EDA,

Mentor Graphics

One year ago activist investor Carl Icahn started a hostile takeover bid for Mentor Graphics and was able to offer up three new board members, however yesterday we read that Mentor Graphics will:

Have their annual shareholder meeting on May 30th
Two of Icahn's board members are not on the roster for renewal
Mr. Icahn has no new board members to offer
...

Read More 10 Comments
IC Reliability and Prevention During Design with EDA Tools

by
daniel_payne
Published on 04-27-2012 03:04 PM

Categories:

EDA,

Mentor Graphics

IC device physics uncovers limits to reliable operation, so IC designers are learning to first identify and then fix reliability issues prior to tape-out. Here' s a list of reliability issues to keep you awake at night:
...

Read More 9 Comments
Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE)

by
daniel_payne
Published on 04-18-2012 10:38 AM

Categories:

EDA,

Mentor Graphics

Smaller IC nodes bring new challenges to the art of IC layout for AMS designs, like Layout Dependent Effects (LDE). If your custom IC design flow looks like the diagram below then you're in for many time-consuming iterations because where you place each transistor will impact the actual Vt and Idsat values, which are now a function of proximity to a well:

Source: EE Times, Mentor Graphics

Analog designs are most sensitive to variations in Vt and current levels, especially for circuit designs that need precise matching.

Engineers at Freescale Semiconductor ...

Read More 6 Comments
Conquering the Big Data Challenges

Published on 04-02-2012 02:38 PM Number of Views: 1279

Categories:

EDA,

Mentor Graphics

Extrapolating the trends from last 20 years to the next ten suggests that we will be implementing a trillion transistors or more by 2020. At 20nm, with the chip sizes touching billions of transistors, the age old problem of how to implement a design in the most efficient manner remains unanswered.

...

Read More 2 Comments
Seminar on IC Yield Optimization at DATE on March 14th

by
daniel_payne
Published on 02-22-2012 01:59 PM

Categories:

Mentor Graphics,

Global Foundries

My first chip design at Intel was a DRAM and we had a 5% yield problem caused by electromigration issues, yes, you can have EM issues even with 6um NMOS technology. We had lots of questions but precious few answers on how to pinpoint and eliminate the source of yield loss. Fortunately, with the next generation of DRAM quickly introduced this yield issue was less urgent.
...

Read More
Will the last 8051 please turn out the lights?

by
Don Dingee
Published on 02-21-2012 12:38 PM Number of Views: 1938

Categories:

EDA,

Mentor Graphics,

Synopsys,

CAST,

Dolphin,

IPextreme

The words no engineer or supply chain professional wants to hear: end-of-life. It's a reality of the semiconductor business, however - even the cheapest parts reach the point, eventually, where producing and selling them becomes inefficient. Is it reasonable that a microcontroller architecture outlive the people who designed it in? ...

Read More 36 Comments
DFM Industry Survey

Published on 02-10-2012 11:28 AM Number of Views: 596

Categories:

EDA,

Mentor Graphics

As part of the DFM Conference at the SPIE Advance Lithography symposium, the DFM committee is conducting an informal survey on the current state of Design For Manufacturability in the Semiconductor Industry.

Please take this anonymous 16 question survey to identify ...

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DFM at SPIE Advance Litho show

by
bmartin
Published on 02-09-2012 04:40 PM Number of Views: 546

Categories:

EDA,

Mentor Graphics

This year’s SPIE Advanced Lithography is loaded with interesting keynotes and sessions. To help me narrow down what to see, I spoke with John Sturtevant. John is co-chair of the Design for Manufacturability through Design-Process Integration conference, and the director for technical marketing for RET products at Mentor Graphics.

12-15 February, 2012
San Jose Convention Center
All the cool kids will be there

...

Read More
Why X-Fab uses 3D Resistance Extraction and Analysis

by
daniel_payne
Published on 02-09-2012 09:18 AM

Categories:

EDA,

Cadence,

Mentor Graphics,

Synopsys,

Foundry,

Tanner

At DAC in 2011 I visited an EDA company called Silicon Frontline Technology because they offered some 3D field solver tools used to create the highest accuracy netlists that can then be simulated with a SPICE circuit simulator to predict timing, power and IR drop. A recent press release with X-FAB and Silicon Frontline looked interesting so I contacted Thomas Hartung, the VP Marketing and Joerg Doblaski, the team leader of the Design Technology Group at X-FAB to better understand their IC design process and why it required a 3D resistance extractor.
...

Read More 9 Comments
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