One of the most useful ways to learn about an EDA tool is to talk with other users that have experience with that tool. IC Place and Route tools are complex and yet necessary to implement every SoC designed today, so at DAC in just two weeks you have a chance to hear first-hand from several P&R tool users. To get a better idea about these P&R users and their IC design challenges I talked with Sudhakar Jilla of Mentor Graphics by phone.


Sudhakar Jilla, Mentor Graphics
...

IC designers involved with physical design are familiar with acronyms like DRC (Design Rule Check), LVS (Layout Versus Schematic) and DFM (Design For Manufacturing), but how would you go about checking for compliance with ESD (Electro Static Discharge) rules? You may be able to kludge something together with your DRC tool and some Tcl or Skill code, but it turns out that there is an easier approach by using a Programmable Electrical Rule Checker. At Mentor Graphics they've dubbed this product as Calibre PERC. I've blogged about PERC before, but I wanted to see what was new and decided to watch an on-demand web seminar where the emphasis was on actually using the tool.
...

Mentor’s announcement from Design West this week pretty much signals the end of standalone ESL tools, in favor of more useful stuff. They have pulled the pieces of their Sourcery CodeBench environment along with their embedded Linux offering and their Vista virtual prototyping platform into a native embedded software development environment.

...

Ground. It’s that little downward-pointing triangle that somehow works miracles on every schematic. It looks very simple until one has to tackle modern power distribution network (PDN) design on a board with high speed and high power draw components, and you soon discover ground is a complicated fairy tale with a lot of influences.

No amount of signal integrity analysis will save a design if the ...

Standard cell library characterization has been around for decades, Synopsys has been offering Liberty NCX and Cadence has Virtuoso Foundation IP Characterization. What's new is that Mentor Graphics acquired the Z Circuit technology for library characterization and has integrated it with the Eldo Classic circuit simulator, along with other SPICE simulators. Today I spoke by phone with Ahmed Eisawy, the Product Marketing Manager for Kronos at Mentor Graphics to get a better idea about their new Kronos tool.


Ahmed Eisawy
...

Those of us who spend a lot of time at EDA marketing events cannot help but notice the dramatic shrinking of the floor space, ...

At the 2010 DAC I moderated a panel session on SPICE and Fast SPICE circuit simulation, and one of the panelists was PierLuigi Daglio from STMicroelectronics. To get an update on SPICE circuit simulation at ST I read a PDF document at Mentor titled: Improving the Quality of SPICE Simulation Results with Eldo Premier at ST.


ST does IC design for many end-markets, like: Home, auto, health industry and ...

Repeat after me: SoCs are paperweights if they can’t be programmed. Succeeding with a new part today means supporting a robust developer program to attract and engage as many creatives as possible. NVIDIA has teamed up with Mentor Graphics in just such an adventure. If you read just the press release, you may have missed the real news.

...

Most embedded programming strategies involve decomposing the embedded application into chunks, which can then be executed as independent tasks. More advanced applications involve some type of data flow, and may attempt to execute operations in parallel where possible.

...