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  • Fractal Technologies

    by Published on 10-21-2014 08:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/12287-crossfire_scheme.gif

    In an ever growing world of IPs, it’s essential that a tool which vouches to simplify designer’s job of IP development and help improving its quality remains versatile to encompass various formats, databases, common data models, standard libraries, scripting etc. that are used in the development of IPs and their exchange ...
    by Published on 08-21-2014 02:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/11861-ds.jpg

    As the SoCs and IPs grow in sizes and complexities, the number of formats, databases, libraries of standard cells and IOs also increase. It becomes a clumsy task to check every cell in a library, its consistency among various format with respect to functionality, timing, naming, ...
    by Published on 06-27-2014 11:26 AM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/11439-rene-donkers.jpg

    Every SoC team uses libraries of cells to get their new product to market quicker: Standard Cells, IO Cells and Hard IP blocks. One immediate question that comes to my mind is, "How clean are these cells?" Validating your cell libraries first makes sense, and will ensure that there are fewer surprises as your chip gets closer to tape-out time. At DAC this year I stopped by the booth of Fractal Technologies and had a conversation with founders Rene Donkers and Johan Peeters to get an update on their EDA business.


    ...
    by Published on 05-28-2014 04:18 PM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/11174-ip-validation.jpg

    In the EDA world we use hyphens quite often to describe our technical approaches, like: DFM-aware, Power-aware, Variation-aware. I just read a white paper today on the topic of Quality-Aware IP Design Flows, written by Fractal Technologies. If your group creates IP or re-uses IP, then there's always the question about the readiness or quality of each IP block. Shown below is a flow of how cell libraries and larger IP blocks get created by an IP vendor ...
    by Published on 04-03-2014 09:32 AM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/10294-crossfire.jpg

    Semiconductor IP continues to grow in use for SoC design, and many chips can now use hundreds of IP blocks from multiple vendors. Validating the quality of the IP blocks is an important step in the design process, and you could perform manual validation and inspection of each new IP block at the expense of time and engineering effort. Another approach is to automate the process of IP validation, and you could start to write your own scripts and create your ...
    by Published on 10-29-2013 09:23 AM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/8923-ecsm-timing-model.jpg

    Semiconductor IP re-use enables modern SoC designs to be realized in a timely fashion, yet with hundreds of IP blocks in a chip the chances are higher that an error in any IP block could cause the entire system to fail. At advanced nodes like 28nm and smaller, the number of Process, Voltage and Temperature (PVT) corners is increasing to account for the variability.

    Qualification of each cell or IP block is then critical to ensure a correct by construction methodology. There are ...
    by Published on 10-17-2013 10:05 AM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/8632-crossfire.jpg

    Imagine that you're working in a CAD group and just received a new library of a few hundred IP blocks and you needed to know if these blocks conform to your design and quality standards. There are many questions about library and IP quality:


    • Are all of the views consistent (layout, schematic, HDL, test, timing, SPICE)?
    • Are there any anomalies in any view?
    • How much time can I spend doing QA on this library?

    ...
    by Published on 06-27-2013 01:34 PM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/7762-img_3477.jpg

    Last year I was surprised at DAC by an un-heard of EDA company from China, ICScape. This year I followed up and spoke with Ravi Ravikumar about what's new with ICScape in 2013.



    ...
    by Published on 06-27-2013 01:13 PM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/7760-img_3475.jpg

    The building blocks for every SoC are standard cell libraries that are assembled, designed and verified together. But how do we really know if all the data formats used during design are correct and consistent? To answer that question I spoke with Johan Peeters of Fractal Technologies at DAC.



    Johan Peeters, Rene Donkers
    ...
    by Published on 06-01-2013 04:00 PM
    1. Categories:
    2. Semiconductor Design,
    3. Fractal Technologies
    content/attachments/7478-renee-donkers.jpg

    Fractal Technologies is a privately held EDA company with offices in San Carlos, California and Eindhoven, the Netherlands. The company was founded by a small group of highly recognized EDA professionals. The scope of Fractal Technologies is to check consistency and validate all different data formats used in your design and subsequently improve the Quality of your Standard Cell Libraries, IO and IP. Fractal Technologies offers Crossfire software as well as services and customization.

    Rene Donkers and Johan Peeters are the gentlemen behind ...
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