As an engineer I learn new concepts best by seeing a demonstration, in this case it was a demo of how to optimize SoC performance by using an ASIC prototyping debug process. SoC designers that use FPGAs to prototype their new ASIC often encounter debug issues, like:

• Limited observability of internal nets required for debug, maybe only 1,000 nets for 1,000 clock cycles
• Adding new internal probes requires a re-run of logic synthesis, causing delays of 8 or more hours
• Partitioning RTL to fit into FPGAs automatically or manually can be error prone, or

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If you design with ARM Cores and need to estimate dynamic power early in the flow, then consider what STMicroelectronics has done with their high performance, power-efficient subsystems. Anne Merlande is a Processor Micro Architecture technical expert, and will be presenting in Booth #1346 at DAC on June 4th, 2:00PM. Her topic is: STMicroelectronics: RTL Power Estimation on ARM Core Sub-systems. You have to register for this suite session.

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My IC design career started at Intel with DRAM chips, so I'm very familiar with clockless design because we used self-timed techniques to get maximum performance. I remember blogging about an asynchronous design company called Tiempo back in 2010, while blogging at Chip Design Magazine. A few weeks ago there was a press release that caught me eye: French Consortium Announces Development of a Clockless SMARTcard chip. Steve Svoboda is my contact at Tiempo and he sent me an email, which turned into a blog interview to satisfy my curiosity.


Steve Svoboda, Tiempo
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I love it when my Acura goes months and months without any major repair issue or computer-related glitches. Cars or networks only become reliable when they are designed and built for reliability. Freescale designs SoCs for advanced automotive and networking applications, and their engineers know much about the topics of power, noise and reliability for these demanding environments.

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Cornelia Golovanov works at LSI Corp in Pennsylvania and is an EMI expert that provides EDA tool and methodology advise to design groups. She earned a PhD in microelectronics and radioelectricity from the Institut national polytechnique de Grenoble, and joined Lucent out of school 12 years ago. We had a chance to talk by phone about her work and also DAC plans.



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At DAC in just three weeks you can learn about which EDA vendors are supporting the latest UVM 1.1d (Universal Verification Methodology) standard as defined by Accellera. One of those EDA vendors is Aldec, and they have a 45 minute technical session that you can register for online. Space will fill up quickly, so get signed up sooner rather than later.
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Thirty years ago in 1983 Professor Daniel Gajski and Kuhn created the now famous Y-Chart to show the various levels of abstraction in electronic system design:



We can still use this Y-Chart today because it still pertains to how engineers are doing their SoC designs. Along the Behavioral axis there is a need to know that each level of abstraction is really equivalent to the other levels to ensure that the design is consistent, ...

Most SoCs today are being prototyped in FPGA hardware before committing to costly IC fabrication. You could just design and build your own FPGA prototyping system, or instead choose something off the shelf and then concentrate on your core competence of SoC design.

Thanks to the FPGA vendors like Xilinx we now have FGPA prototyping platforms that can reach over 100 million ASIC gates in capacity at a reasonable cost. Aldec has created ...

The tremendous growth in IC and SoC design complexity has now enabled engineers to place bilions of transistors on a single chip. To make that growth possible design teams resort to using libraries and semi IP provided by other groups in their company, or outside IP vendors. To lower risk, you must know that the IP being used in your next SoC is correct and that no errors are present.

You could create ...