• Register
  • Help
SemiWiki

  • Home
    •  
  • Forum
  • Wikis
  • Seminars
  • EDA
    • Apache Design Inc.
    • Atrenta
    • Berkeley Design
    • Cadence
    • Ciranova
    • ClioSoft
    • Jasper DA
    • Magma DA
    • Mentor
    • Pulsic
    • Runtime Design Automation
    • Sagantec
    • Solido DA
    • SpringSoft
    • Synopsys
    • Tanner EDA
  • Design IP
    • Arasan
    • Arteris
    • PerfectVIPs
    • Synopsys
    • Tensilica
    • TSMC
  • Services
    • Global Unichip Corp.
  • Foundry
    • GlobalFoundries
    • TSMC
  • FAQ
  • About
  • Advanced Search
  • Home
  • Home
  • The Front Page

  • Recent Articles

    Daniel Nenni

    Smartphones and Tablets Thirst for Bandwidth!


    The explosive growth in portable devices over the past decade has left manufactures in a quandary over how to add memory to their products that meet several criteria:
    • High capacity
    • Low cost
    • Low power
    • High bandwidth

    ... read more
    Daniel Nenni 4 Days Ago
    Daniel Nenni

    Semiconductors: A Decade of Invention... A World of Solutions

    Please join IBM, Samsung Electronics, Co., Ltd., and GLOBALFOUNDRIES at our 2012 Common Platform Technology Forum. The forum will showcase the alliance’s technological progress and how joint collaboration and innovation is setting the direction for industry-leading solutions to enable next-generation products.

    ... read more
    Daniel Nenni 5 Days Ago
    daniel_payne

    What Just Changed On My Transistor-Level Schematic?

    Digital designers have used diff tools for years on their text-based HDL source code, but what about for transistor-level IC designer, where is their diff tool for schematics?
    ... read more
    daniel_payne 6 Days Ago

    Categories:

    EDA 
    daniel_payne

    Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS

    Ken Kundert while at Cadence developed: Spectre, Spectre RF, Verilog-A and Verilog-AMS. About 6 years ago he and Henry Chang left Cadence and created a consulting company called The Designers Guide.

    ... read more
    daniel_payne 1 Week Ago

    Categories:

    EDA  Cadence 

    DFM Provides Proven Value

    Although design for manufacturing (DFM) tools and techniques have been around for several nodes, a lot of designers remain skeptical about their actual value, especially since many products still make it successfully to market without the use of DFM.
    ... read more
    1 Week Ago
    Paul McLellan

    Power to the Drones

    Unmanned systems are becoming indispensable to military forces and are used across all of land, sea and air. The generic name for such unmanned systems is UXS, usually UAS (air), UGS (ground) or UUS (underwater). The UAS is the most visible, both due to military strikes and the views of Japan after the Tsunami when areas were unreachable by... read more
    Paul McLellan 1 Week Ago

    DFM Industry Survey

    As part of the DFM Conference at the SPIE Advance Lithography symposium, the DFM committee is conducting an informal survey on the current state of Design For Manufacturability in the Semiconductor Industry.



    Please take this anonymous 16 question survey to identify... read more
    1 Week Ago

    Categories:

    EDA  Mentor Graphics 
    Paul McLellan

    Yes, there is such a thing as a free...model

    I have been saying for years, ever since I started working at VaST, the biggest barrier to adoption of virtual platform technology for what I like to call virtualized software development is the availability of models. If models do not already exist when they are needed there are two issues: it takes money to develop them but, probably more importantly,... read more
    Paul McLellan 1 Week Ago
  • daniel_payne

    PLL Design Challenges for Integrated Circuit Designs 

    by
    daniel_payne
    Published on 02-20-2012 08:54 AM
    1. Categories:
    2. EDA,
    3. Cadence
    content/attachments/2902-nandu-bhagwan.jpg.html

    Nandu Bhagwan is CEO of GHz Circuits and has been designing PLL circuits used in ICs for the past 12 years. Mr. Bhagwan did a video interview with John Pierce of Cadence to talk about the challenges of PLL design.
    ...
    Read More Read More

    Magma FineSIM and MunEDA Cooperate 

    by
    daniel_payne
    Published on 02-17-2012 03:06 PM
    1. Categories:
    2. EDA,
    3. Magma
    content/attachments/2883-muneda-gmbh.jpeg.html

    How do I know if an AMS block is tuned for the process and will perform and yield acceptably?
    ...
    Read More Read More 3 Comments

    What Just Changed On My Transistor-Level Schematic? 

    by
    daniel_payne
    Published on 02-16-2012 08:05 AM
    1. Categories:
    2. EDA
    content/attachments/2848-screen-shot-2012-02-09-4.04.15-pm.jpg.html

    Digital designers have used diff tools for years on their text-based HDL source code, but what about for transistor-level IC designer, where is their diff tool for schematics?
    ...
    Read More Read More 3 Comments

    Words of AMS Wisdom from the Developer of Spectre, Spectre RF, Verilog-A, Verilog-AMS 

    by
    daniel_payne
    Published on 02-15-2012 08:27 AM
    1. Categories:
    2. EDA,
    3. Cadence
    Article Preview

    Ken Kundert while at Cadence developed: Spectre, Spectre RF, Verilog-A and Verilog-AMS. About 6 years ago he and Henry Chang left Cadence and created a consulting company called The Designers Guide.

    ...
    Read More Read More 4 Comments

    Why X-Fab uses 3D Resistance Extraction and Analysis 

    by
    daniel_payne
    Published on 02-09-2012 09:18 AM
    1. Categories:
    2. EDA,
    3. Cadence,
    4. Mentor Graphics,
    5. Synopsys,
    6. Foundry,
    7. Tanner
    content/attachments/2837-thomas-hartung.jpeg.html

    At DAC in 2011 I visited an EDA company called Silicon Frontline Technology because they offered some 3D field solver tools used to create the highest accuracy netlists that can then be simulated with a SPICE circuit simulator to predict timing, power and IR drop. A recent press release with X-FAB and Silicon Frontline looked interesting so I contacted Thomas Hartung, the VP Marketing and Joerg Doblaski, the team leader of the Design Technology Group at X-FAB to better understand their IC design process and why it required a 3D resistance extractor.
    ...
    Read More Read More 9 Comments

    Using "Apps" to Take Formal Analysis Mainstream 

    by
    daniel_payne
    Published on 02-02-2012 10:47 AM
    1. Categories:
    2. EDA,
    3. Cadence,
    4. Semi IP
    Article Preview

    On my last graphics chip design at Intel the project manager asked me, "So, will this new chip work when silicon comes back?"

    My response was, "Yes, however only the parts that we have been able to simulate."

    Today designers of semiconductor IP and SoC have more approaches than just simulation to ensure that their next design will work in silicon. Formal analysis is an increasingly popular technology included in functional verification.

    DVCon 2012


    I received notice of DVCon 2012 coming up in March, and saw a tutorial session called: Using "Apps" ...
    Read More Read More 3 Comments

    Design & Verification of Platform-Based, Multi-Core SoCs 

    by
    daniel_payne
    Published on 02-02-2012 09:16 AM
    1. Categories:
    2. EDA,
    3. Mentor Graphics,
    4. ARM
    content/attachments/2759-amazon-kindle-fire.jpg.html

    Consumer electronics is a new driver in our global semiconductor economy as we enjoy using Smart Phones, Tablets and Ultra Books. The challenge of designing and then verifying the electronic systems to meet the market windows is a daunting one. Instead of starting with a blank sheet for a new product, most electronic design companies are choosing to start with a platform then integrate ready-built IP.



    Amazon Kindle Fire - Tear Down

    An example of a platform-based ...
    Read More Read More 2 Comments
    Page 1 of 16 12311 ... Next LastLast
  • Upcoming Events

    ISSCC (San Francisco, CA)

    02-22-12

    Hardware/Software Co-design from a Software Perspective (San Jose, CA)

    02-27-12

    DVCon 2012

    02-27-12

    UFS Webinar with Arasan Chip Systems

    02-29-12

    UFS Webinar with Arasan Chip Systems

    02-29-12
  • Recent Forum Threads

    vepuri

    process design development

    Thread Starter: vepuri

    hiiii

    Recently i got selected in one MNC company and they had mentioned my work will be in process design kits development department..could

    8 Hours Ago by vepuri Go to last post
    Paul McLellan

    Semiconductor Technologies for 2012

    Thread Starter: Paul McLellan

    Every year, Wright Williams & Kelly, Inc. (WWK) conducts a survey on equipment and timing of various features in the semiconductor industry. The

    5 Days Ago by khhsu Go to last post
    Daniel Nenni

    Synopsys / Magma Acquisition Debate!

    Thread Starter: Daniel Nenni

    The calls and emails are still coming in for more information on the SNPS / LAVA acquisition: Magma customers, ecosystem partners, lawyers, and even a

    16 Minutes Ago by Daniel Nenni Go to last post
    gauravjalan

    Verification IP : Changing landscape

    Thread Starter: gauravjalan

    For decades, EDA industry has been working out options to improve their offerings and ensure silicon success for the semiconductor industry. A few decades

    1 Week Ago by gauravjalan Go to last post
    daniel_payne

    PLL Design at GHz Circuits Inc - Video Interview

    Thread Starter: daniel_payne

    Nandu Bhagwan is the President and CEO of GHz Circuits, Inc. In this video interview with John Pierce of Cadence he talks about PLL design challenges.

    1 Week Ago by daniel_payne Go to last post
    daniel_payne

    Video Interview with Triune Systems, a fabless design company doing AMS

    Thread Starter: daniel_payne

    Dave Stone and Ross Teggatz of Triune Systems talk with John Pierce of Cadence.

    Triune Systems is a fabless semiconductor company that

    1 Week Ago by daniel_payne Go to last post
    daniel_payne

    Video Interview with the developer of the Spectre Circuit Simulator

    Thread Starter: daniel_payne

    Ken Kundert wrote the Spectre Circuit Simulator while at Cadence, he's now President at Designer's Guide Consulting. Here's a video interview with Ken

    1 Week Ago by simguru Go to last post
    Daniel Nenni

    Taiwan trip Report!

    Thread Starter: Daniel Nenni

    My trip to Taiwan this week was very productive. 28nm yield, 20nm challenges, 2011 review, 2012 strategies, this will be a very good year for the semiconductor

    1 Week Ago by khhsu Go to last post
    Daniel Nenni

    DesignCon 2012 Trip Reports (iPad2 Giveaway)

    Thread Starter: Daniel Nenni

    SemiWiki will give another iPad2 to a member that participates in this thread. Post a trip report or if you are not able to attend post your thoughts

    2 Weeks Ago by Staf_Verhaegen Go to last post
  • Contact Us
  • SemiWiki
  • Archive
  • Top
All times are GMT -8. The time now is 01:59 PM.
Copyright © 2012 SemiWiki.com. All rights reserved.
Legal Disclosure.