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  • AMS Design at AnSem

    EDA - a four-letter word?-screen-shot-2011-10-19-1-49-23-pm-png
    AnSem has been in the AMS design business since 1998 and uses a variety of commercial EDA tools along with internally developed tools and scripts to automate the process of analog design and technology porting. Their IC designers have completed some 40 AMS projects in diverse areas like:
    • RF CMOS
      • LNA, VCO, Mixers
      • Synthesizers
      • Low-IF/Zero-IF

    • Low Power / Low Voltage
      • 1v wireless TRx
      • Power management
      • Battery operation

    • Data Acquisition
      • Sensor interfacing
      • A/D
      • D/A

    • High Speed Data Communication
      • SerDes
      • Line driver/Receiver
      • PLL, CDR

    EDA - a four-letter word?-layout02-jpg

    Commercial EDA Tools

    Best in class is the tool selection methodology used at AnSem, with the following EDA tools used for specification, design, optimization and verification:

    High level modeling and verification - Matlab Simulink

    Top down modeling, bottom up design - VHDL-AMS using Mentor's Questa ADMS (Eldo, Eldo RF, ADiT). This can be used for models of a receiver, demodulation and PLL circuits.

    Digital Simulation - Mentor's Questa (ModelSim)

    Transistor layout and sizing - Internal tools, Tanner EDA (L-Edit, HiPer Layout)

    IC Layout - Cadence Virtuoso

    Internal EDA Tools
    One of the internally developed tools is called AnSem Advanced Proprietary Synthesis Tool (APST) and it fits into the design flow to develop analog cells for the purpose of design re-use and technology porting. Building IP that can be re-used at new nodes is achievable with APST. The transistor sizing done by APST is used in the Tanner EDA tools.

    PLL designs are optimized with a tool called PLLOP. RX noise gain and blocking analysis is performed by a tool called MREX. Finally, there are application-specific Matlab toolboxes created to automate tasks like FSK demodulation.

    Automated IP
    AnSem engineers have created many IP blocks with an automated design approach:
    • VCO with on-chip integrated inductors
    • LNA with on-chip inductors
    • Delta-Sigma A/D: switched-cap
    • Comparator: High Speed, Flash
    • OTAs and OpAmps for low-frequeny
    • OTA-C filters for active-RC type circuits
    • Bandgap reference circuits

    Experience with Tanner EDA Tools
    EDA - a four-letter word?-screen-shot-2011-10-19-2-32-45-pm-png

    AnSem first started using the Tanner EDA tools right from the start in 1998 because they could design their IP blocks and use the tools at a reasonable cost. Today the designs can target even the 40nm node and the design complexity has increased significantly.

    Using schematics and layout from Tanner in Cadence Virtuoso is now possible with the Open Access (OA) database. Interoperability is an important trend for EDA tools and has provided AnSem some flexibility. Customers of AnSem user different IC tools so working with industry standards like OA meets the need.

    Learning the Tanner tools was intuitive as they are based on the popular Windows operating system and GUI. Designers can extend the features of the tools by scripting, all without having a specialized CAD department.

    DRC and LVS are done with Tanner and the rules from Mentor's Calibre tool are imported.

    AnSem has assembled both commercial and internal EDA tools to automate their AMS design for both ASIC and custom IC design work. Customers of AnSem include: Tyco Electronics, Oce Technologies, Phonak, Cochlear, Kawasaki Microelectronics, National Semiconductor and NXP.