Mentor Graphics and GLOBALFOUNDRIES have been working together for several generations since the 65nm node on making IC designs yield higher. Michael Buehler-Garcia, director of Calibre Design Solutions Marketing at Mentor Graphics spoke with me by phone today to explain how they are working with GLOBALFOUNDRIES on a 3rd generation DFM (Design For Manufacturing) flow.
3rd party IP providers like ARM and Virage have been using this evolutionary DFM flow to ensure that SOCs will have acceptable yields. If the IP on your SOC is litho-clean then the effort to make the entire SOC clean is decreased. GLOBALFOUNDRIES has a mandate that their IP providers pass a DFM metric.
Manufacturing Analysis and Scoring (MAS)
In box A of the flow shown above is where GLOBALFOUNDRIES measures yield and the yield modeling info needed to give Mentor the design to silicon interactions. This could be equations that describe the variation in fail rates of recommended rules, or defect density distributions for particle shorts and opens.
Random and Systematic Defects and Process Variations
At 100nm and below nodes there are both random defects and process variations that limit yield. Critical Area Analysis (CAA) is used for random defects and Critical Failure Analysis (CFA) is used for systematic defects and process variations. These analysis help pinpoint problem areas in the IC layout prior to tape out.
DRC+ Pattern-based Design Rule Checking Technology
Patterns that identify low-yield areas of an IC can be defined visually then run in a DRC tool like Calibre.
Litho Friendly Design (LFD)
Calibre LFD accurately models the impact of lithographic processes on “as-drawn” layout data to determine the actual “as-built” dimensions of fabricated gates and metal interconnects. There are new LFD design kits for the 28nm and 20nm nodes at GLOBALFOUNDRIES.
Calibre LFD uses process variation (PV) bands that predict failure in common configurations including pinching, bridging, area overlap and CD variability.
In the early process development of 20nm the foundry uses Calibre LFD to predict the hot-spots and then create the design rules.
Place and Route
Integration with the Olympus-SOC™ design tool enables feed-forward of Calibre LFD results to give designers guidance on recommended layout improvements, and to enable revalidation of correct timing after modifications.
Foundries, EDA vendors and IC design companies are collaborating very closely to ensure that IC designs will have both acceptable yield and predictable performance. GLOBALFOUNDRIES and Mentor Graphics continue to partner on their 3rd generation DFM flow to enable IC designs at 28nm and smaller nodes. AMD is a leading-edge IC company using the Calibre DFM tools on the GLOBALFOUNDRIES process.
To learn more about how Mentor and GLOBALFOUNDRIES are working together you can visit the Global Technology Conference at the Santa Clara Convention Center on August 30, 2011