Cadence Verification IP Technical Seminar!

According to trusted sources it costs upwards of $50M to design a 40nm SoC down to the GDS. Semiconductor IP is a fast growing part of that equation and functional verification of that IP is critical. Hardware complexity growth continues to follow Moore’s Law but verification complexity is even more challenging. In fact, IP verification is widely acknowledged as the major bottleneck in SoC design. Up to 70 percent of the design development time and resources are spent on functional verification. Even with such a significant amount of effort and resources being applied to verification, functional bugs are still the number one cause of multi million dollar silicon re-spins.



Cadence Verification IP Catalog Technical Seminar
Join us for an in-depth look at Cadence Verification IP Catalog. In this seminar we will hear case studies from experts in the field addressing your most challenging issues when it comes to verifying today's most important interfaces such as AMBA4 ACE, PCIe Gen 3, USB 3.0, DDR4 and more.

Case studies will focus on real world scenarios and be interactive in nature. In this seminar you will also hear how Cadence with Denali offers the most comprehensive, flexible and open solution on the market for verifying and integrating IP.

August 25, 2011 - Cadence Design Systems (San Jose - Bldg 10 Auditorium), San Jose, CA
1:00 PM - 4:15 PM Pacific

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