Speeding Verification of FPGA Prototype Boards
It is no secret that SoC designs continue to increase in complexity and time-to-market windows are shrinking. While there is room for debate on just how big a fraction of SoC design effort goes on verification, there is no debating that it is a large part of the total.
Simulation is increasingly too slow, especially when software has to be verified against the hardware. In some areas, formal techniques can be attractive but they are not universally applicable. One attractive approach is to use FPGAs to build a prototype of all or part of the SoC use this for verification. However, one big challenge is that synthesis, place and route for an SoC-sized FPGA can take as long as a day. It is impossible to observe every signal in a large SoC and so the SoC must be re-synthesized each time that a change is required in which signals need to be kept track of. Full re-creation of all the layout each time a change is made in the choice of signals is too slow. ProtoLink Probe Visualizer is a new approach to the problem. By understanding the placement and routing within the FPGA it is possible to make changes incrementally and almost instantaneously. With the addition of an interface containing probe memory, the data that it is possible to collect goes from 10s of signals for limited cycles, with a one day turnaround on changes to the signal list, to thousands of signals for millions of cycles, with a few minutes to update the list. The whitepaper is here