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  • RLCK reduction tool at DAC

    Most EDA parasitic extraction tools have built-in RC reduction with no user control however at DAC I learned how Edxact offers a stand-along RLCK reduction tool for IC designers that want more control over what happens to their extracted netlists.

    EDA Mergers and Acquisitions Wiki-dac-edxact.jpg
    Daniel Borgraeve (on right)

    - Started seven years ago
    - Fifteen people in the company
    - Based in France
    - Jivaro: RLCK reduction (RLCC) with user control of results
    o Many algorithms to choose from
    o Used by Aglient in their GoldenGate tool (RF Simulator)
    o Used by Intel
    o About 25 customers world wide (Asia, Japan, Korea, US)
    o Part of TSMC AMS Reference flow 2.0
    o Pricing starts at $100K per license per year
    EDA Mergers and Acquisitions Wiki-jivaro-graph.jpg

    - Comanche:
    o Read parasitic
    o Create R values point to point, calculate delays
    o CAD developers can compare two netlists (Golden versus some extraction tool)
    o Parasitic analysis platform
    o Used by: AMD, ST Ericsson
    o Pricing starts at $100K per license per year
    - Partners
    o Altos (Library Characterization, used Jivaro)
    o Cadence (Integrated into Virtuoso)
    o SpringSoft (Integrated into Laker, can annotate parasitic into Laker)
    o Mentor (read DSPF, Eldo formats)
    o Synopsps (support Star RC and HSPICE syntax)
    o TSMC part of AMS Reference flow
    - Runs on: Solaris, Linux, Mac

    If you want more control while reducing RCLK netlists then consider looking at Edxact tools.

    This article was originally published in forum thread: Best #48DAC Trip Report Gets an iPAD2 started by admin View original post