You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • EDA Interoperability at DAC

    My Wednesday breakfast at DAC last week was at the Interoperability event sponsored by Synopsys. The Synopsys moderator was so jovial that he reminded me of Jerry Lewis, I was relieved when the guests gave us an update.
    SPICE, Fast SPICE and Analog Fast SPICE-dac-snps-wed-breakfast.jpg

    Interconnect Modeling
    - Open Source Interconnect Technology Format (ITF)
    o Used by Star RC
    - Modeling parasitic of interconnect
    - Interconnect Modeling Technical Advisory Board founded, meet twice per year
    o Program of IEEE-ISTO
    o Andy Brotman, VP Design Infrastructure at GF
    IMTAB – foundry perspective
    Design starts are slowing in number for each new node (although each new node has more devices)
    Need to avoid risks, ensure 1st silicon success
    Mistakes are more costly (NRE)
    Parasitic variation increases at 20nm, more analysis required
    Layout effects need to be simulated earlier
    Best in class extraction tools are a must
    Standard interconnect tech file used (Star RC, F3D, …)
    New layout effects: Orientation dependent width bias
    o Rich Laubhan, Engineer and Manager of Signal Integrity at LSI Corporation
    User perspective (Used Star RC for 13 years now)
    LSI products: HDD controllers, SSD controllers, RAID adapters, networking
    Producing 65nm, 40nm, 28nm chips
    Many signoff PVT/RC corners
    • No real single corner to simulate
    Many modes to simulate: functional, scan, BIST, TDF
    High speed designs: 500MHz to 2GHz clocks
    Can have 200 clock domains
    Hierarchical designs with 20M instances
    Plot of transistor feature size and number of metal layers (12 layers now)
    ITRS plot: total metal interconnect on a chip over time, more resistive effects
    No standard test structures to measure R L C values
    We use Charge based capacitance measurement (CBCM)
    More wires, higher resistance, metal fill effects: designer challenges
    LSI Design Flow: Tech File and Design input to Parasitic Extraction, output a SPICE Or SPEF file
    • Tech file: cross section, dielectrics, vias, R L C values
    Tech File Complexity: IC Cross section with 12 metal layers, dielectrics
    • Longer qualification time to meet accuracy goals
    • Variation in process causes variation in R L C values
    ITF Open source – provides a proven format with support from 130nm to 20nm
    ITF Extensions proposed
    • Quick process to get ratified
    • Layout dependent effects
    • TSV
    • 28nm and 20nm effects
    Desire to use fewer EDA tool formats to keep costs lower
    • Changed extraction tools three times for last three technology nodes
    • Agreement on test structures
    • Accurate results
    Tenzing Norgay Award
    - Surpass common levels of interoperability
    - Contribute to overall industry advancement
    - Provide a new view of the future
    - 2011 Winner: Shreink Mehta
    o Work on UPF, SystemVerilog
    o Sun SPARC
    o OVI and VHDL
    o SPIRIT

    IPL & Custom Design
    - IPL Constraint 1.0, first standard for interoperable analog design constraints
    - OPDK and iPDK are cooperating
    - Vincent Varo, Process Design Kit Manager, STMicroelectronics
    o Desire to reduce effort in PDK development, create one PDK not many, use across all EDA tools
    o Device Library, DRC, LVS, PEX, SPICE
    o Standardized input to PDK development process from all foundries desired
     Standard DRM, Device Specification format
    o Challenge: How to validate an automatically created PDK?
    o Mulitple methods to create a single iPDK
    o Parasitic Extraction technolog file
     IMTAB, or Si2 OPEX WG
    o Desire to be EDA Tool independent
    o Next steps
     Automate the PDK validation process
     Design re-use and portability
     AMS design portability
     Designs that are DRC and LVS clean by construction
    - Ori Galzur, VP VLSI Design Center, TowerJazz
    o Largest foundry for speciality technologies
    o Total of 4 foundries: Newport Beach, Japan, Israel, China
    o Approaching $1B in revenues
    o Power, BiCMOS, SiGe, RF CMOS, Image Sensor, Mixed-Signal CMOS, eNVM
     1um to .13um
    o Specialty PDK for high voltage process
     Automatic device scaling based upon the voltage levels that you need
     ESD rules added to PCELL
     From schematics a designer gets to choose from a GUI all of the device parameters
    o Average PDK has over 120 devices
    o Each device can be used in: Standard, Shallow NBL, Deep epi
    o All devices are voltage scalable, optimized
    o Supporting multiple tool sets takes too much engineering effort
    o Want one PDK to focus engineering on other value add efforts
    o Choose the best foundry, best EDA tools, not locked into a vendor-specific PDK
    - Demand that your Foundry and EDA vendors support iPDK

    This article was originally published in forum thread: Best #48DAC Trip Report Gets an iPAD2 started by admin View original post