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  • Blue Pearl at DAC

    It's all about analyzing RTL and creating timing constraints at Blue Pearl, so I stopped by their booth on Tuesday morning to get an update on what's new for 2011.

    Semicoductor Market Outlook in 2011 - 2012-technology1.jpg


    What’s New in 2011 at Blue Pearl Software

    New designer experience, ease of use. Brand new GUI.

    Work with RTL to synthesis tools to get best timing in your layout.

    GUI – windows 7 and Linux, same look and feel.
    - All new in 2011
    - Inline help

    Blue Pearl Analyze – Linting, race checks,
    - Demo: support languages: verilog 1995, 2001, 2005, System Verilog, VHDL 2008
    - Read your libraries
    - Modules can be grey box or black box
    - Clocks can be automatically identified or manually setup
    - Schematic view auto generated based on your source code
    o Cross probe between RTL and schematic view
    o Quick browsing of hierarchy
    - About 250 checks are run on the source code
    o LInting
    o Low power
    o Timing constraints
    o DFT
    o CDC
    o Etc
    - Visual Verification
    o 200K gate design
    o Lint, structural checking, CDC analysis, CDC identification,
    o Using FlexLM for licensing
    o False path, multicycle paths
    o Only 45 seconds needed on a laptop
    o Faster than others who synthesize to gates, instead of staying at RTL level
    o About 10X faster than other approaches (Atrenta)
    o Run the tool from the bottom up
    o All the CDC unsynched paths are shown in text list, clicking creates a schematic view
    o Designer decides what to do with the violations to accept or ignore
    o User can filter the messages, warnings, errors (Use rules, patterns, modules, names, severity)

    Blue Pearl Create –
    - Creates an SDC file automatically
    - All false paths are displayed in a tree view and schematic view
    - Assertions are shown for each false path
    - An audit trail explains why the control values are creating a conflict
    - The SDC file will help other tools (STA, Synthesis, ATPG) to reduce their run times
    - Can save weeks of time compared to manual SDC constraint generation
    - 200K design run in minutes
    - Customers: Microsoft, KLA, Cypress Technologies

    Usage: Block level designs, run on PC or Linux boxes

    Users: IC (Constraint generation), FPGA (Help on large designs like Virtex with 10M gates, PC and Windows. Find Clock Gating opportunities), IP (want more tool flexibility)

    Version 5.0 (Blue Pearl Software Suite)

    This article was originally published in forum thread: Best #48DAC Trip Report Gets an iPAD2 started by admin View original post