Frederik Iverson AE
Scott Wetch HSPICE Architect
HSPICE 5 years ago convergence was not so good, while 95% of analog circuits today converge out of the box, no options are required.
Synopsys AMS Portfolio wide range of tools
- Custom Designer: IC schematic and layout tools
- HSPICE circuit simulation
- CustomSim full chip circuit simulation
- IC Validator/Star RC extraction, DRC, LVS
HSPICE Golden SPICE standard for about 30 years now, the same tool the foundry used to create their cells
- Used in IC, AMS, PCB for SI
Issues Long run times, could be days to cover all of the corners required, more runs
Improvements in HSPICE 5X faster than 2007 on a single core, averaged over 100s of circuits
- Precision Parallel, 7X faster when using 8 cores compared to a single core
- 10X more capacity, about 10 million elements
- New Analysis added: High Frequency, Statistical Eye Diagrams, Transient Noise, Loop Stability
- Convergence, 95% out of the box, no settings required
- Distributed Processing (MC, Corners, Sweeps) distribute over the network (17X on 20 CPUs)
HSPICE Precision Parallel run times reduced from days to hours
- Up to 7X faster on 8 cores (use hpp option)
- PLL runs now reduced to 4 hours instead of days
- PLL example with 7K MOS and RC, 12.5 hours (148 hours, competitor)
- Clock Tree with 10M elements, 7 hours (108 hours, competitor)
- Sigma Delta Converter, 7.7 hours (16 hours, competitor)
HSPICE Distributed Processing divide and conquer (MC, corners with .ALTER, sweeps)
- 10 CPUs at 8.7X faster
- 20 CPUs at 17.3X faster (some overhead to collect all that data)
Post-layout selective net back-annotation (use parasitic only where needed)
- Check and find only the active nets for extraction (automatic or manually identified)
- Apply parasitics only to critical nets that are identified
Transient Noise Analysis Include noise in time domain simulations (about 2X to 3X slower than transient)
- Full nonlinear analysis of noise effects in the time domain
- All devices are taken into account (thermal noise, channel noise, flicker noise)
- Today a single CPU, in September see the parallel version
Custom Designer (Schematics and Layout)
- HSPICE integrated within
Frederick Iverson, demo of Duty Cycle Corrector (40nm node, Used in IP group for USB 3.0, 450 analog designers at SNPS)
- Custom Designer uses OA for a db. Any circuit simulator can be added to Custom Designer.
- Normal simulation is 5 minutes to complete, Precision Parallel completes in about 1 minute
- Command line has Tcl, so its easy to save and re-run commands.
- Si2 is showing how to run tools with many languages: Tcl, Perl, Ruby, etc.
- Plot of simulation results shown in WaveView tool, measurement tool to show % duty cycle.
- HSPICE uses one license for two threads, so use it at no extra cost
- Back annotate a full netlist or a partial netlist (used a DSPF file from Star RC)
- Names in HSPICE are the pre-layout names even with back-annotated values
- Transient noise demonstrated, the output does show jitter, wave view shows jitter versus time, histogram shows standard deviation on jitter values
HSPICE has to continually improve in order to stay current with Berkeley DA, Eldo, Spectre and FineSIM circuit simulators.