Back in the day I knew the founders of Artisan (VLSI Libraries) when we worked together at Silicon Compilers (Mark Templeton, John Malecki, Scott Becker).
Q: Do you favor any EDA tools for creating your IP?
A: No, we dont really endorse a specific EDA vendor tool or flow.
Q: What's new at ARM for 2011?
A: Just started Process Optimization Packs. Linking IP that is tuned for ARM cores.
Artisan Generic cells. Used to wait for a node to become stable.
ARM Focused on leading edge cells, now at 28nm nodes. Now doing test chips quite early to tweek and optimize cells, as requirements into the process.
2010 32nm last year announced.
2011 28nm IP is now ready as soon as announced. TSMC, SMIC, Samsung, IBM, GlobalFoundries (CP), TSMC.
Q: How to reach Power Performance and Area for your design?
A: We have a User Guide on how to get best results.
Q: Any preference for PDKs?
A: Support whatever PDK is available, no preference.
Synopsys renewed tools agreement for a period of time.
Cell Library about 1,000 cells to choose from, with about 100 different functions. Simple gates, flip-flops (power saving modes)
Q: What is your royalty model?
A: Royalty Model same as always, no upfront costs. Foundries pay for library development.
Memory compilers cells Standard RAMS, then lower VDD RAMs for an extra price. Typically 5 to 7 compilers per node.
Foundries Some are offering their own libraries.
ARM Artisan IP (re-using)
Memory Compilers Virage (Synopsys) has a piece of it. ARM invests heavily in these at leading edge nodes. Area efficient nodes too.
SOI French based (SOISIC), acquired about 5 years ago, used at IBM.
Physical GP IOs, 40nm Low Power. Will add DDR libraries soon. Have controller, PHy and IO in one piece.
Q: What do you think of Intel's TriGate?
A: FinFET At 20nm planar CMOS still works, 14nm then FinFET looks viable.
Q: What is success for ARM?
A: Success We think rich solutions across a wide range of foundries at 28nm now, 20nm soon (test chips with Samsung).
Q: How do you use RDR?
A: RDR Weve been dealing that for a few nodes now (20nm needs double patterning). We work closely with foundries for all nodes.
Common Platform ARM is the IP you get.
Q: Where do I find out more?
A: Visit our SOC Design Community