You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • FineSIM adds RF Analysis plus new Tcl Circuit Checks

    At DAC I spent time in the Magma FineSIM demo suite on Monday morning.

    Greg Curtis – Product Director, Custom Design Business Unit
    EDAC CEO Forecast Event Report!-dac-magma-finesim.jpg
    - Talus for Digital Design
    - FineSim does: SPICE, FastSPICE, Characterization
    - Flows Demoed at DAC: High Performance Core, SOC, ASIC/ASSP, AMS, Memory
    - What’s New in FineSim?
    o RF
    o TCL circuit checks
    - ADC design trends
    o Parasitics dominate performance now
    o Sensitivity to noise and cross talk
    o Operating at low power
    o Requires more SPICE, more corners, more analysis
    - Cell phone trends
    o 10+ radios per phone
    o Maximum battery life
    - FineSim SPICE
    o Multi-cpu and multi-machine capability
    o Standard netlist inputs (HPSICE, ELdo, Spectre)
    o ER and IR drop analysis
    o Co-simulate with Verilog and VHDL
    o New:
     Tcl based circuit checks (interactive simulation)
    • Customized check that you write to check currents, voltages, timing
    • Set breakpoints
    • Demo: find all outputs above 2.6V
    • Demo: At 5th rising edge, wait 25ns, capture signals, check sum of currents, trigger if >50uA used
    • Could write Tcl code to calculate the jitter of a PLL real time during simulation
    • Technology could traverse a netlist similar to Calibre PERC, but not there yet
     RF Analysis (Harmonic Balance, Periodic AC Analysis, Periodic Noise, Periodic Transfer, Oscillator Phase Noise)
    • Multi-CPU capability
    • Due in November 2011
    • Beta in September 2011
    • A new option to FineSim SPICE
    • Demo of a 9 stage ring oscillator
    o One CPU run first, 25 seconds
    o Four CPUs run next, 12 seconds
    o FineWave used to show the waveform results
    o AC wave, phase noise plot shown
     EM/IR Analysis
    • Titan is being used for EM/IR Analysis
    • Demo of NAND gates in a layout and schematic
    • Titan uses the Analog Simulation Environment (AVE)
    • EM/IR analysis results viewed on top of the layout using color codes, layout zoomed in when clicking on a specific EM/IR result
    • Capacity is a few million MOS devices
    o 1.5X Faster than Berkeley (PLL)
    o 1.4X faster than Cadence APS (Sigma Delta Modulator)
    o 5X faster than Eldo
    - FineSim PRO
    o Multi-rate engine, hierarchical processing (but not hierarchical simulation)
    o Same features as FineSim HSPICE
    o Capacity example had only 4.6M devices
    o 7.9X to 16X faster than NanoSim, Hsim,XA (under 2M MOS devices)
    Improvements:
    - 2011.04 release versus 2010.08
    o 1CPU, 7.5% less memory. 1.23X run time improvement
    Foundry Support
    - TSMC, GlobalFoundries, TowerJazz, Lfoundry

    Customer Usage:
    - 12 of top 20 Semiconductor companies using FineSIM
    - Analog Bits, 10X speed up wit FineSim
    - ESNUG user: 3X to 10X over HSPICE

    Anand Ganesan – Senior Product Engineer (demonstrations)

    Summary
    FineSIM catches up to HSPICE, Eldo and Spectre in simulating RF circuits.

    The Tcl Circuit Check looks similar to the technology in Mentor's Calibre PERC. Let's see if they create a product to detect ESD best practices like PERC does.

    This article was originally published in forum thread: Best #48DAC Trip Report Gets an iPAD2 started by admin View original post