But we can design in such a way for this growth rate become more modest, even if the number of equipment (the servers) is still rocketing. Using the very last PCI Express configuration can help, for example. Just take a look at the PCIe gen-3 Controller IP core launched by Cadence, exhibiting several power friendly features:
- Innovative circuit calibration technique in new Cadence® PCI Express® 3.0 solution enables customers to meet aggressive active power goals.
- Advanced power and clock management capabilities reduce standby current by 100X
- Optimized transition time latency between active and sleep states
The IP (and EDA) company has realized that datacenters are only running at peak usage 20 percent of the time. Their PCIe solution has been designed to provide optimal energy efficiency during these peak usage times, as well as during idle times, to address these datacenter industry challenges. With the additional support of the latest low-power PCIe L1 PM Substates Engineering Change Notice (ECN) across all Cadence PCIe IP, Cadence is able to provide both low power and high performance during peak operation and system power savings during idle operation. Looks pretty simple, like any brilliant idea!
In fact, Cadence has implemented the latest evolution of the PCIe gen-3 specification, as explained by said Al Yanes, PCI-SIG president and chairman. “The PCI Express L1 PM Substates ECN provides significantly improved power savings over the current L1 Substates, and helps bring improved energy efficiency to a vast array of platforms. Member companies like Cadence provide important IP solutions to allow SoC developers to fully exploit the power efficiency mechanisms provided by our flagship PCIe architecture.”
The new PCIe IP from Cadence supports x16 configuration, giving designers the maximum performance along with virtualization support to service multi-threaded applications. For those who are not very familiar with PCI Express technology, a 16 lanes Controller supporting gen-3 is able to transmit (and receive, at the same time, as the protocol is dual simplex) up to 16 times 8 Gigabit of data, if you prefer 16 Giga Bytes per second! “With datacenters responsible for two to three percent of worldwide energy consumption, advanced technology like our new PCIe IP can have a significant impact for our customers and end consumers,” said Martin Lund, senior vice president, SoC Realization Group at Cadence. “Leveraging Cadence’s many years of high-speed SerDes design, our new PCIe 3.0 controllers and PHY will help our customers reduce leakage power consumed by the PCIe interface from milliWatts to microWatts.”
I was told that Cadence’ PCIe PHY exhibit a very aggressive power consumption by lane, like for example a 70 mW value in a 8 lanes configuration, including the PLL. In fact, the more lanes you are able to share using the same PLL, the lowest power consumption by lane you will exhibit. If you compare this value with the figures from 2005, where a PCIe PHY was designed in 90 or 65nm, supporting 2.5 GT/s only (gen-1), you realize how better we are today: the gen-1 PHY in 2005 exhibited 100 mW (or 40 mW per GT) when Cadence PHY exhibit 70 mW divided by 8 (GT) or less than 10 mW per GT. The industry has been able to divide by 4 the power consumption per data transferred, in 8 years.
If you follow the news in the mobile industry, you have noticed the emergence of Mobile Express, or M-PCIe, where the PCIe Controller is used with a MIPI M-PHY, to benefit from the lower power consumption of this MIPI PHY. The Mobile industry is obviously “low-power friendly”, so it’s interesting to notice that cadence also support M-PCIe, most probably with a different controller architecture than for the server industry, we will come back later of this very promising new protocol, and comment the latest news…
By Eric Esteve from IPNEST