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  • Full Chip IR Drop Analysis using Distributed Multi Processing

    IR drop analysis across your board, package and SoC ensures that your Power Delivery Network (PDN) is robust, and that your system will function to spec. There are both static and dynamic approaches to IR drop analysis of a full-chip with billions of transistors, while the dynamic approach produces the most accurate results compared to silicon behavior. Apache has been providing IR drop analysis tools for about a decade now, and Aveek Sarkar spoke with me this afternoon about how they have used Distributed Multi Processing (DMP) to scale up the analysis.

    Article: Cadence ClosedAccess-aveek-sarkar.jpg
    Aveek Sarkar, Apache

    Q & A

    Q: When did you start at Apache?

    I've been at Apache for 10 years now, and am employee #12.

    Q: What are the challenges of IR drop analysis?

    One challenge is how to compute the actual Idd and Iss currents from board to package to chip, because these values are time-dependent.

    Global IR drop analysis is required, it cannot be divided into smaller blocks. Other types of analysis can be divided into smaller pieces that are then sent to different CPUs.

    The IR drop challenge is not solved by divide and conquer in our approach.

    Consider an SoC with an ARM CPU plus a GPU, these IPs can have different VDD nets but can end up sharing the VSS net - so they are connected electrically, and therefore cannot be partitioned for IR drop analysis.

    The effect of package and board must be taken into account with the IC, so all three levels must be simulated together.

    Q: How is your approach different for IR drop analysis?

    We partition our anlaysis while keeping the global effects intact, so we call our approach DMP - this uses a cluster of machines. We see very similar results on a clustered approach as compared to a single CPU when run flat. There is less than a 3% difference, while the DMP capacity is 3X bigger, and run time is 2X faster (versus full-flat analysis).

    We're using smart-partitioning, where the integrated effect is taken into account. The Redhawk tool user just uses the Cluster on their design. At the end of analysis you get to visualize the results in the GUI, seeing the entire results and the result looks just like a flat analysis.

    Article: Cadence ClosedAccess-3d-ic-voltage-drop-using-multi-pane-gui.jpg
    Redhawk - 3D IC Voltage Drop Analysis, GUI

    Q: How do I know the proper size cluster to use?

    RedHawk has an explorer feature which will recommend the machine requirements. Our factory also consults with ASIC customers to recommend the best cluster.

    Q: How do i know if Redhawk results are accurate?

    You can build and measure silicon to convince yourself of the accuracy. Companies like AMD have presented at DAC this year where silicon results were provided, with good correlation to simulated.

    Q: What is the status of Redhawk using DMP technology?

    DMP is in early use as Beta right now, our 2nd level of customers will be added by December, and by DAC next year we will be in production release.

    We typically have two product releases per year.

    Q: How similar is IR drop analysis to SPICE circuit simulation with transient analysis?

    They are very similar electrical ideas in terms of current and voltage calculations. We linearize the problem and make it a scalable problem using DMP. We could have 1+ billion nodes to solve, and we do it efficiently. We do a very accurate time-domain analysis going down to time-step of say 5ps or so.

    Q: How much analysis speedup should I expect with my cluster of CPUs?

    The analysis speedup is sublinear, so going from 4 to 16 CPUs will show less than 4X speed improvement given the nature of the problem we solve.

    Q: How do I start an evaluation of Redhawk using DMP?

    For an evaluation contact me at the factory.

    Article: Cadence ClosedAccess-scw13-bnnr_1000x120.jpg