On Tuesday afternoon at DAC I attended a luncheon presentation with the following four speakers:
- Dave Reed, Synopsys
- KC Change, Richtek
- Yu-Yuan Tseng, Meditek
- Masataka Sato, Fujitsu
Notes from June 4, 2013
Dave Reed, Synopsys
1,000+ internal IP designers doing analog and custom IC designers using Synopsys tools.
600 R&D with Magma/SpringSoft/SNPS.
Mixed implementation - both Digital (IC Compiler) + custom IC
Fast to create custom layout.
Golden simulation (HSPICE), and extraction (Star RC)
IC Compiler Co-Design : IC Compiler plus Custom Designer at any time in the design process (twisted pair, matched length, shilded clock, shielded bus)
- shape-based routing (acquired), Galaxy Custom Router
Front end schematics - Custom Designer
IC Layout - Laker Layout, both use OA and same PDK, unified, working together. SDL - schematic driven layout.
- Launch HSPICE, FineSim, CustomSim, waveform analysis.
- In Laker call up IC Validator for LVS, use extraction with StarRC
- in SDL the schem/layout views can have different hierarchies
KC Chang, Richtek. VP of Technology Development
Mature nodes for Big A, little D.
Used Matched device creator (use layout patterns)
- If you build it, they will come. Founded in 1998, sales of $1.495 B NT. 849 employees, analog product focus for consumer market. Top 10 PMIC supplier ww, and #1 in Asia. Power converters, power controller, battery charger. Analog chips used in Panel display, smart phones. Computing, Communication and consumer markets.
Using: Laker Schematic, Laker Layout, reusable IP library, std cell library, Mcells, Pdevices (Tcl program). Added use of SDL in 2006. Created our own High Voltage devices using Mcells, making Laker user extendible.
- created their own PDK for high voltage requirements, supporting device matching and guard rings.
Using Laker SDL With Mcell methodology we are saving 40% of IC layout time.
Doing mostly Big A, Little D chip designs. Small, custom digital blocks can be added in our layout flow, replacing manual P&R flow (weeks to hours).
Wants - analog prototyping with analog P&R features.
Yu-Yuan Tseng, MediaTek
For 20nm design have built-in DRC is a must have for DPT compliance.
MediaTek is a fabless IC design company with 6,900 employees worldwide, products in wireless, optical, digital home, mobile phone chips.
Started using Laker in 2000, SDL in 2003, started at 250nm while now at 20nm and 16nm nodes.
Manual DRC debugging in batch mode is just too slow, so now using real time DRC checks interactively instead of batch mode. At 20nm we have too many new layout rules and DPT, decided to use LiveDRC (show DRC errors, show fixing guide, show DRC rules).
- Customize Rules for flexibility.
DPT issues - misalignment of two masks impacts RC extracted values. You can constrain a critical net to use a single mask, not allowing two masks.
Using both Laker schematic and Laker layout in a DPT flow. Saving about 35% on IC layout time by using the LiveDRC approach.
Room for improvements: same rule deck with LiveDRC and IC Validator.
Masataka Sato, Fujitsu
Integration with DRC/LVS tools, Star RC and IC Validator
SRAM design engineer, doing 20nm technology node. Reduced our IC layout time by about 50% by using Laker tools.
Fujitsu Semi does design, development and manufacture of: Mobile, Automotive infotainment, Imaging in Camera/TV/phones, Server/networking.
Plan to have their 20nm design into prototype this year, and production next year.
SRAM goals: high speed, low power, small area, quick time to deliver.
SRAM layout challenges: full manual layout times, DPT, local interconnect.
Laker - stable IC Layout editor, Tcl interface for automating commands like arrays of cells.
- quick to measure distance without zooming, alignment automation feature.
- bundled buses are easy to create and label.
- In-design DRC with other tools (Calibre?)
TAT improved by 50% using Laker, mostly by the in-design DRC
Power device group using MCell.
FCRAM team using DRC real time, Pycell, OA with other tools.
View the videolog: