At DAC last week I met with Neal Carney to get an update on what Tela Innovations is up to this year.
Dhrumil Gandhi (left), Neal Carney (right)
Power reduction benefits - gate length biasing to reduce leakage, (Blaze MO) analyze slack in non crtical paths then swap out for lower drive cells and lower dynamic power. Non disruptive to design, because the layout is smaller. Can reduce up to 15% on dynamic power. Works on a timing-closed design
SOld to COT users or provided as a service. Published users are LSI Logic, Mellanox - network processing, Mindspeed - now defunct.
TSMC (Power Trim) - using Tela technology.
Litigation ongoing now.
FinFET - still could use this approach with multi VT.
All the data in chart is bulk CMOS, not FinFET or FD SOI (yet).
Concurrent Leakage and Dynamic Power Reduction
Litigation - no news until settlement or agreement reached.