You are currently viewing SemiWiki as a guest which gives you limited access to the site. To view blog comments and experience other SemiWiki features you must be a registered member. Registration is fast, simple, and absolutely free so please, join our community today!

  • ARM SoC Hardening

    Last year at DAC I discovered a physical IP company called DXCorr that competed against giant ARM. This year the company has selected a different direction, so I got caught up with Nirmalya Ghosh, the CEO to hear about the changes.

    Article: Layout for analog/mixed-signal nanometer ICs-nirmalya-ghosh.jpeg
    Nirmalya Ghosh, DXCorr

    Q: How is business for DXCorr?

    A: It has been an awesome year for DXCorr. The company headcount stands at close to 60 now and we just moved to a shiny building in Bangalore.

    Article: Layout for analog/mixed-signal nanometer ICs-new-building.jpg

    Q: What is new this year for DXCorr at DAC?

    A: We are slowly positioning ourselves as the best "ARM SoC hardening house in the world".

    Q: ARM is a popular architecture, how do you achieve good SoC hardening results?

    A: We achieve this using our proprietary RTL level floorplanning tool called DXPRO which seamlessly interfaces with mainstream EDA P&R toolset and with our very own Physical IP (memories, register files, CAMs, standard cells).

    Article: Layout for analog/mixed-signal nanometer ICs-dxpro.jpg
    DXPRO - Placement and Routing Optimization Tool

    Q: How is your design service different than what others can offer?

    A: We strongly believe, the way we are handling the power-aware RTL placement, no one else is doing that.

    Q: What kind of QoR can you achieve with your SoC hardening?

    A: We believe we can save roughly save 20% of active power off an ARM SoC implementation this way.

    Q: Where can people find you at DAC?

    A: We're in booth #733 this year.

    DXCorr is a provider of leading edge physical IP solutions for advanced semiconductor process technologies. DXCorr’s products meet the needs of performance-oriented, low-power SOC designs and include advanced memory IP such as SRAMs, CAMs, multi-port memories and memory subsystems as well as differentiated standard cell solutions. DXCorr also provides PDK and PCELL development for analog and mixed-signal designs and RTL to GDS design services.

    Article: Layout for analog/mixed-signal nanometer ICs-dac2013banner-reg.jpg