N. Kannan from Freescale in New Dehli, India agreed to be interviewed for SemiWiki, and he is manager of the Physical Design Flows. Kannan has been working with the central Flows and Methodology team of Freescale Semiconductor since 2004. During the course of his work, he has lead key initiatives across the company in the areas of Layout parasitic Extraction and Power Integrity.
He will be presenting at Booth #1346 at DAC on Monday, June 3rd at 1:00PM on: Power, Noise and Reliability Consideration for Advanced Automotive and Networking ICs.
Q: What kind of SoC designs does your group work on?
A: Our company has a varied portfolio, but the main product areas on which this presentation will focus on will be SoCs for Automotive and Networking applications.
Q: What is your role on the team?
A: I am currently manager of the Physical Design Flows & Methodology team in Freescale India. My technical focus area has been in the domain of Power Integrity and was playing a key role in aligning and supporting this flow across product groups in Freescale global teams. As part of this, I was required to work with both the design teams and collateral providers to align the tool and flow across the design spectrum.
Q: Tell me about your design challenges.
A: The two product groups, due to the nature of the design requirements, face different challenges. The automotive SoCs though smaller in die-size need to grapple with the complexities of on-chip flash and a high percentage of on-chip analog IPs and factoring in their effect on Power Integrity. The multitude of power domains as well as low power requirements pose their own challenge. Also, close interaction is needed with the board designer to ensure EMC compliance.
The Networking products have to grapple with the challenges of multi-Core SoC implementation and very high speed and low clock skew requirements. The design sizes are a big challenge and also the high speed interfaces require very heavy involvement of the Power grid designer with the package design team. Package design to meet heat dissapiation is a common challenge, albeit the focus from automotive perspective is to reduce package costs, while for Networking products the high power consumption requires careful analysis of the heat disappiation.
Q: Which Apache tools are you using?
A: Primarily Redhawk (dynamic power integrity) and Totem (full-chip, layout-based power and noise) and the associated utilities. Evaluation has been also carried out on Sentinel Thermal (Chip-package-system thermal) analysis, ESD Pathfinder (Electro-static Discharge) and PowerArtist (RTL-based power analysis).
Q: How do the Apache tools fit into your overall EDA tool flows?
A: The Apache tools are our primary tools for Power Integrity signoff on advanced technology nodes.
Q: How do the Apache tools help your design team?
A: These tools serve designers during the various stages of design implementation to help meet above mentioned challenges and sign-off on the Power Integrity and Reliability.
Q: What other approaches did you try before using Apache tools?
A: We have had a mix of internal and third party tools in the past.
Q: What was the learning curve like to become proficient with Apache tools?
A: While the tools are stable, by sheer nature of the flow being worked on, the designer is required to spend effort to get a handle on the tool and use it as per her requirements. Features like Redhawk Explorer help in debugging design issues faster.
Q: What is support like from Apache?
A: The best part of the Apache support has been the high level of technical understanding and the desire to provide a complete solution to our needs instead of just limiting the engagement to tool features.