Q: What kind of SoC designs does your group work on?
A: My group provides Tools and Methodology to the Design teams in various business units, like Storage Components which designs products for markets like:
- Host Bus Adapters
- 6Gb/s SATA+SAS RAID Controller Cards
- 3Gb/s SATA+SAS RAID Controller Cards
- 6Gb/s SAS Switch
- SandForce Flash Storage Processors
- Nytro Application Acceleration Products
- Syncro Shared Storage
- Standard Product ICs
- Hard Drive SoCs
We select and qualify EDA tools used from the front end to back end, and sign-off.
MegaRAID SAS 9280-24i4e
Q: What is your role on the team?
A: I provide methodology and training and a lot of hands on help with System level Power and Signal Integrity analysis
To all business units: Storage in the HDD business, the server storage business Raid SD and to the Flash Components business.
Q: Tell me about your design challenges.
A: Moving my internal customers from an SOC0centric design flow to a more system-aware design flow.
In other words having them insist on getting and then using accurate models of the world outside of the SOC, like the package and PCB, or the connectors and DDRs.
Another challenge is the interference between power supplies on an SoC. We use dedicated power supplies per macro block. For example, PLLs are sensitive to power variations, so we used dedicated supplies for those blocks ande we use an Apache tool called Sentinel to help model the interference between IO rings and the PLL block.
Q: Which Apache tools are you using?
A: I am using CPM models (Chip Power Models) from Redhawk in the system level PDN (Power Delivery Network) analysis and adopted recently Sentinel SSO to model simultaneously switching outputs (SSO).
My talk at DAC will be on Sentinel which really provides a bridge between SI and PI in general But brought real palpable relief in two particular crisis situations we recently faced.
Q: How do the Apache tools fit into your overall EDA tool flows?
A: From my perspective, actually perspectives because I looked at this integration from two different vintage points : from the pre-layout perspective where you only have the IOs chosen and have their models but don’t have anything else, not even the PG rails and you look to see how much noise would your IO ring couple into the PG on PCB and package and then I also looked from the post-layout perspective using a database primed for tapeout,
with a spotless PG rail sign-off.
So from these two extreme vintage points the Apache suite seems an easy landing, you just bring your GDS (which is generated for TO anyway), and bring the various LEF files. Bring a ploc file to list the location of the PG pins at top level and Apache hooks the system parts together for you. Then you provide Ansys/Ansoft package/pcb models.
Our design flow is Synopsys on the front end, sign-off is both Synopsys and Apache. There is good Apache/Ansoft integration, where SiWave and Apache work together smoothly, even a bi-directional flow.
Q: How do the Apache tools help your design team?
A: Apache tools help integrate the system model into the die sign off analysis, and help getting a more accurate model of the behavior of the load the SOC is seeing at its pads.
Q: What other approaches did you try before using Apache tools?
A: In debug mode we relied a lot on measurements. In preventive mode we tried using models extracted with Ansoft tools in HSPICE and Spectre circuit simulations
Q: What was the learning curve like to become proficient with Apache tools?
A: It seems pretty intuitive when a skilled AE teaches it to you on a design and a situation that you are very familiar with. It lets you focus on the tool and it makes it really easy to understand why you do what you do, the sequence of operations when reading data in, the sequence in which the various simulations are layered.
And that was always our model with Apache, the initial evaluation of a tool is always done by them on one of our real full-size designs.
Q: What is support like from Apache?
As I was just saying, they are excellent in launching one on their orbits! They’re so good that they can make you look proficient the first time you run an analysis on your own…
Q: When is your presentation at DAC this year?
A: I'll be presenting at Booth #1346 on Tuesday, June 4th at 3PM, the title is: Chip and I/O Modeling for System-Level Power Noise Analysis and Optimization.