You could create some incoming tests on your re-used IP, or maybe even buy some Verification IP (VIP). There's a three year old EDA start-up called Fractal Technologies that has a tool that help you test the quality of IP by:
- Reporting mismatches or modeling errors for Libraries and IP
- Do all schematic pins occur as terminals in layout and abstract views?
- Are all delay arcs from Liberty present in Verilog?
- Can all pins be routed in first-metal?
- Is a reset pin active-low in SPICE, Verilog, and .lib files?
- Does the LEF abstract correctly cover the layout view?
- Do all cells abut?
- Check on presence and contents of cell- or pin-properties?
- Verify that certain pins are located correctly within a cell?
- Checking view consistency (ECSM, CCS)
- Are CCS peak currents increasing with capacitance?
- Are cell delays increasing with increasing temperature and decreasing supply voltage?
- Checks occurence and correctness of cells, pins and terminals
- Cross-checks delay tables, delay path conditions, setup and hold-times
- Checks consistency of Liberty characterization data
- Checks routability requirements on cell terminals
- Checks functionality descriptions
- Checks layout representations
- Checks can be coded by end-users in popular scripting languages
This checking technology is called Crossfire and it works with industry standard formats:
- LEF, DEF
- GDS II, Oasis
- OA (Open Access)
- Liberty NLDM, NLPM, NLNM, CCS, CCSN, ECSM
- Milkyway from Synopsys
- Verilog, SystemVerilog, Verilog AMS, VHDL
- Timing Library Format
- FastScan, Tetramax
- STIL/CTL (Core Test Language)
If you are a group that creates or uses Libraries or semi IP, then using this technology would improve your quality in a shorter time.
At DAC you can see the folks at Fractal Technologies in booth #1617, ask for Rene Donkers.