- Industry keynote: Keith Klarke, VP Embedded Processor, ARM
- Industry keynote: Rudi de Winter, CEO X-FAB
Extracted from their web site: “X-FAB manufactures wafers for automotive, industrial, consumer, medical, and other applications on modular CMOS and BiCMOS processes in geometries ranging from 1.0 to 0.18 µm, and special BCD, SOI and MEMS long-lifetime processes.” X-FAB market positioning is not to compete head on with TSMC or GlobalFoundries on 28 nm technologies, but to serve growing market segments like automotive and industrial, requiring mature technology nodes supporting high voltage or/and high current.
Keith Klarke, from ARM, will deliver the second keynote talk after Lip-Bu Tan. This is a good indication about the IP strategy that Cadence is building: Tensilica IP will not be used to compete with CPU or GPU IP cores from ARM, but rather could be integrated within ARM based architecture. We can imagine, for example, an integrated AP/BB chip implementing ARM Cortex big.LITTLE CPU architecture and LTE modem based on Dataplane customizable processor from Cadence/Tensilica imtegrated together. As Tensilica Dataplane also supports many other application like audio, voice and speech or image/video processing, to name a very few, there will be room for cooperation… and also for competition. By having ARM VP giving a “Industry Keynote” talk right after Cadence CEO is certainly a sign that Cadence prefers cooperation with ARM, which is by far the most realistic approach: the MIPS recent history has shown that the market don’t really need “another RISC CPU core family”, but rather a complementary offer. L
ike I write in Semiwiki a couple of years ago, ARM ubiquity has been built on the long term, is now based on a 1000 partners Ecosystem and an essential customer installed base. Will such a status change in the near, or even far, future? Competing head on with ARM would require such an amount of energy, time and resource, that I don’t see Cadence (or Synopsys) to initiate such a battle. Staying partners is certainly the wiser solution!
CDN-Live is a three day event, with an equivalent two days agenda, and covers from mixed-signal full custom, to digital, IP and Verification based design, up to PCB, signal integrity or power aware design. On May 8, Hardware/Software, as well as chip/package co-design and system-level design will be covered. That day will also include presentations made by users from Freescale, Renesas, ST-Microelectronics, ZMD, Infineon or Amkor. During the event there will be tutorials made by cadence and Academic presentations from various Universities in Europe. This should be a dense event!
To Register to CDN-Live, just go here
On my side I will focus on the Design and Verification IP tracks, with a special attention about Interface IP: PCIe and M-PHY, USB 3.0 PHY IP, Memory Models for Verification and DDR SDRAM Memory Controller and PHY IP. It will also be a good opportunity to learn about Tensilica Dataplane CPU and I am sure not to miss that track, as I will make the presentation just before, named “Interface IP protocols: the winners, the losers in 2012”. It will be strongly updated from the presentation made during IP-SoC last December in Grenoble, as many changes have occurred during Q1 2013! Because
we can now take into account the 2012 actual IP sales results for the various protocols (DDRn, USB, PCIe, SATA, MIPI, Ethernet, Thunderbolt, HDMI, DP), it will be fresh information, in advance from the launch of the “Interface IP Survey”…
Eric Esteve from IPNEST