Q) Tell me about your design background at PMC Sierra.
A) I worked there and we designed chips for optical networks, SONNET switching, multiplexors, etc. Lots of analog content plus SoC. It was built with Standard Cell and full-custom analog front-end for optical receivers.
I did some block level design, then moved up to higher levels of abstraction. We acquired a company called Toucan Technology in Ireland and I visited them to help get their first chip designs completed.
Our validation lab required lots of work to make certain that the reliability levels were achieved.
Q) Why the switch from design to CAD tool development by joining Altera?
A) After PMC Sierra I started my PhD work at UBC. At Altera they wanted to do timing correlation between FPGA and structured ASICs. It was really just a consulting contract.
Q) What kind of design did you do at Teradici?
A) They had a specific design problem where I worked on the first generation PCI-Express and high-definition audio sub-system. We also designed the second generation PCI-Express. I did both consulting and full-time work for Teradici.
Q) Why did you choose UBC in Vancouver, Canada to study?
A) I was looking for specific professors, and I had read about Steve Wilton and Res Saleh (founder of Simplex). I was doing consulting while getting my Ph.D.
Q) Why did you start your own company, Veridae Systems?
A) I did PhD research at UBC on embedded instruments that were flexible, light weight, and powerful. It seemed like it could be commercialized, so I licensed the technology from UBC and started up Veridae Systems. In the early days it was Steve Wilton, Res Saleh and myself that founded the company.
We didn't know much about starting up a company, then I took over the CEO role and learned the business side. I met Jim Derbyshire, and he was mentoring many university-based start-ups, then helped us get started.
We grew the company for two years, with the first year creating a product for FPGA debug. We learned from early customers what they really wanted. Tektronix came along after we had a product, then offered to acquire us and do the sales and marketing.
Q) What lessons have you learned since joining Tektronix?
A) We knew from our days at Veridae that certain companies will not deal with a startup, so now that we were inside of Tektronix these companies now trusted us. On the product side we've learned more about what FPGA designers want out of a debug tool, so we know how debug can be done more pro-actively by inserting probes pro-actively, saving iteration time. This is a very different approach than what other tools have taken.
I like the flexibility of living in Vancouver, and then visiting the Tektronix HQ in Beaverton, Oregon as needed.
Q) Are their any competing approaches to the Certus technology in use today?
A) Sure, the competitors are using things like Emulation for debug where you can see all the internal signals, though quite pricey. You can also take the internal FPGA data off chip to an external memory for post-processing like Synopsys, while Certus uses on-chip memory with compression.
Q) What makes Certus so different from any other debug approach?
A) Our approach works on any FPGA architecture, no special connectors are required. We offer really deep trace depth, where you can probe 10,000+ signals to debug, then start to focus on the signals of interest. Other approaches cannot handle 10,000+ signals for debug.
Q) What is the technology direction for Certus in the future?
A) One big trend is to higher levels of abstraction. We see designers today using Certus and giving them a good view of their RTL, however they really want to trace issues up to the software level. Tracing more signals, like 200,000 is a constant request with low impact.
Q) What is your proudest technical achievement, and why?
A) The very first sale of Certus, to actually go from an idea to real product worth buying.