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  • Another Winner at DesignCon

    After a show like DesignCon wraps up we get a chance to ask ourself what it all meant, and how was this year different than last year. Reading through many posts about DesignCon I came to discover that the Awards at DesignCon are less contentious than at CES, and also that ANSYS received a DesignVision award for the 2nd year running. Their winning tool in the category of Modeling and Simulation is called HFSS for ECAD.

    Article: TSMC Versus Intel: The Race to Semiconductors in 3D!-ansys.jpg

    Typically the design engineer doing PCB layout would use Cadence tools, then export their design data, ask the SI expert to import them into a field solver like HFSS, setup and run the field solver, interpret the results, and communicate verbally with any recommendations. Not a very productive flow, so the process has been integrated quite a bit.

    Article: TSMC Versus Intel: The Race to Semiconductors in 3D!-cadence-apd-ansys-link-menu.jpg

    You can now stay working in your familiar Cadence layout tools and launch HFSS for analysis:

    • Allegro PCB Designer
    • Allegro Package Designer
    • SiP Layout
    • Virtuoso Layout Suite

    The software that enables this integration is called:

    • ANSYS HFSS, or HFSS solver-only option
    • ANSYS Designer Pre-Post, or ANSYS DesignerSI
    • Ansoft Links for ECAD

    Article: TSMC Versus Intel: The Race to Semiconductors in 3D!-cadence-allergro-ansys-link.jpg

    Using this combination of ECAD tools from Cadence and field solver tools from ANSYS lets engineers design and quickly analyze chip, package or boards where you need a 3-D model to take into account high-speed interconnect or complex packaging structures. The manual steps have been eliminated and the setup streamlined, so that you can stay in the Cadence tools to run field solver jobs like:

    • HFSS port drawing and setup
    • Automated clipping of nets
    • Setup of HFSS meshing frequency
    • Frequency sweep type, and range setup
    • HFSS convergence criteria
    • Solver and basis function selection
    • Airbox definition

    Article: TSMC Versus Intel: The Race to Semiconductors in 3D!-virtuoso-spiral-layout.jpg

    If you want to save some time and agony, then consider looking at this integration between Cadence and ANSYS tools for your chip, board and packaging design challenges where a 3-D field sovler is required. I'm glad that Mark Ravenstahl of ANSYS talked with me two weeks ago about what to look for at DesignCon in 2013.

    Article: TSMC Versus Intel: The Race to Semiconductors in 3D!-20nm-ref-flow-banner.gif