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  • Cadence sets the Global Standards in VIP for AMBA based SoC

    We have shown in Semiwiki how strong Cadence position was in Verification IP (VIP) in a previous post focusing on Interface standards like SuperSpeed USB or PCI Express. But IP based functions are used everywhere in a SoC, not only to interface with the external world, and need to be verified, as well, like for AMBA based functions. Cadence has worked closely with ARM to ensure its VIP solutions support ARM CoreLink™ CCI-400 Cache Coherent Interconnect and CoreLink NIC-400 Network Interconnect using the AMBA 4 protocols. Using Network on Chip (NoC) is now common for SoC design, even if the concept is no more than 10 years old, and using a Cache Coherent Interconnect is recommended when the SoC is using multiple processor cores. Then comes the need for a proven, flexible and highly differentiated verification solution for ARM CoreLink interconnect IP, including the most advanced AMBA specifications such as AXI4 and AXI Coherency Extensions (ACE), that Cadence propose with various verification products dedicated to Non Coherent Interconnect (AXI4, AHB or APB VIP) as well as Cache Coherent Fabric with AXI Coherency Extensions (ACE) VIP.

    Article: TSMC Versus Intel: The Race to Semiconductors in 3D!-cadence-soc-diagram-small.jpg

    Looking at the customer list for a specific product often tell you more than looking at the product brief itself. For example, Cadence proudly mention three customers, HiSilicon, Faraday and Ceva, for the ACE, AXI4 and AXI VIP, each of these customers designing SoC for a specific application, each of them having his own careabouts.

    HiSilicon is the chip design company affiliated to Huawei, involved in leading edge Network Processor or Set Top Box SoC design, requiring high computational power, often multi-core based. As most of you probably know, Huawei is now one of the leaders on this market, and HiSilicon demand is for a stable, proven VIP solution to successfully verify the performance of the SoCs. Standard VIP has been used, allowing to verify a complex design as fast as possible to allow for the best Time To Market.

    Article: TSMC Versus Intel: The Race to Semiconductors in 3D!-ceva.jpg

    CEVA, the market leader in DSP IP, had a different need. As we can see in the above picture, CEVA was developing a complete sub-system including their XC4000 core, plus Program memory and Data memory subsystems and the related L1 program and data caches, and related Emulation functions (ICE). To best optimize this XC4000 Architecture, CEVA was using an internally modified AXI protocol. Because the interconnect IP was modified, the standard Verification IP from Cadence could not be used as is, but Cadence and CEVA have worked together to modify the AXI Verification IP, in order to be able to completely run verification on the XC4000 DSP subsystem. Flexibility from Cadence has allowed deriving an effective VIP solution to support CEVA specific needs.

    Article: TSMC Versus Intel: The Race to Semiconductors in 3D!-pic_engagement_01.gif

    Faraday, providing ASIC design services and subcontracting SoC design to various customers, is another example of a successful partnership, Cadence bringing AMBA AXI Verification IP product, and Faraday designing various type of SoC for customers targeting UMC technology.

    If we come back to the image at the top, we notice on the right side a block named “Interconnect Validator”, sounding like the tool could have been used in Star War environment. In fact, Cadence Interconnect Validator verifies the interconnect fabrics that connect IP blocks and subsystems within an SoC. Whereas a principal aim of verification IP (VIP) is to verify that IP blocks follow a given communication protocol, Interconnect Validator verifies the correctness and completeness of data as it passes through the interconnect. It’s just like if R2D2 will soon work in place of the designer! Because it automates a critical, yet difficult and time-consuming task, Interconnect Validator greatly increases verification productivity at the subsystem and SoC levels. This is the type of tool which is expected to greatly speed-up the TTM for complex SoC, reducing the time dedicated to Verification, known to be longer than the pure design task, probably in the 2/3rd to 1/3rd proportion. If you want to have a look, just go to Interconnect Validator page.


    • AMBA protocol support: ACE, AXI4, AXI3, AHB and APB
    • OCP 2.0 protocol support
    • Supports verification at the subsystem and SoC levels
    • Supports any number of master ports, slave ports, and interconnect
    • Enables verification of hierarchal / cascaded fabrics
    • Enables verification of non-standard interconnect

    Interconnect Validator works in conjunction with VIP components to model and monitor all ports on an SoC’s interconnect. Sophisticated algorithms track data items as they are transported through the interconnect to their destinations. Arbitration of traffic is accounted for as well as data transformations such as upsizing, downsizing, and splitting.

    Cadence has built a page dedicated to AMBA AXI4 Verification IP, where you will find some of the customer testimonials mentioned in this post, as well as nice video, one of them from Mirit Fromovich, in charge of the World Wide deployment of AMBA Verification IP, who I thank for her support in helping me to better understand these complexes VIP…

    Eric Esteve from IPnest

    Article: TSMC Versus Intel: The Race to Semiconductors in 3D!-20nm-ref-flow-banner.gif