Cadence and TSMC have a long history of collaborating to deliver solutions that ensure our joint customers’ success. Along with design ecosystem partners such as ARM, Cadence and TSMC team up on TSMC’s Open Innovation Platform to optimize design and manufacturing efficiencies to ensure your design’s success.
While at TSMC OIP 2012, be sure to schedule your time to catch all the activities and sessions that Cadence is hosting. Here is your schedule for all things Cadence at OIP.
At 12:30, enjoy lunch courtesy of Cadence, your official lunch sponsor for TSMC OIP 2012.
After the morning keynotes, Cadence will deliver detailed technical sessions in both the IP and EDA tracks.
- 11:30 AM: How to Manage Variability and Double Patterning at 20nm (EDA track)
- 2:00 PM: 3D-IC Silicon Interposer IC Design Flow Using Cadence Encounter Digital Implementation (EDI) System (EDA track)
- 3:30 PM: TSMC Certification for Cadence 20nm RTL-to-GDSII Flow (EDA track)
- 4:00 PM: Enabling Design with Advanced Node Design IP for TSMC (IP track)
- 5:00 PM: Using Latest-Generation DDR4, LPDDR3 and Wide-IO DRAM Devices with Chips in TSMC's Advanced 28nm and 20nm (IP track)
Cadence demonstrations will be available throughout the day. Visit Cadence in Booth 414 to see demonstrations of how Cadence and TSMC collaborate to help you optimize PPA. Demonstrations include:
- 3D-IC Design Infrastructure Enablement Supporting CoWoS
- Virtuoso 20nm Certified Technologies
- 20nm Certified High Performance Technologies
- Custom Design Qualified Reference Flow
- Certified Signoff Technologies for Advanced Nodes
- Design IP for DDR4 and 28nm
Win a Kindle Fire Visit two demo stations in Cadence booth 414 and have your entry form from your registration bag stamped at each demo station. Drop off your completed entry form at Cadence booth 414 before 6:00PM. The winner will be drawn before the end of the networking reception.