Aldec-Altera DO-254: How to Increase Verification Coverage by Test

As described in DO-254, any inability to verify specific requirements by test on the device itself must be justified, and alternative means must be provided. Certification authorities favor verification by test for formal verification credits because of the simple fact that hardware flies not simulation models. Requirements describing FPGA I/Os must be verified by test. The problem is that testing the FPGA device at the board level provides very low FPGA I/O controllability and visibility, therefore, giving you the inability to verify specific requirements by test.

In this webinar, Aldec will demonstrate how you can verify all FPGA level requirements by test. All of the requirements verified during simulation can be repeated and verified in the target device. We will demonstrate a unique solution that enables requirements-based test by reusing the testbench as test vectors for testing the device at-speed.

In this webinar, Altera will also share insights into the market trends observed from different applications and discuss some of the solution strategies that will address the system reliability concerns. Using the Altera-Aldec partnership as an example, Altera invites collaboration and partnership to address the industry needs.

Live Webinar Presenters
Louie De Luna, Aldec DO-254 Program Manager
Ching Hu, Altera Military BU, Sr. Marketing Manager

US Session Date: September 27, 2012 Time: 11:00 am - 12:00 pm Pacific Daylight Time (USA) Register for US Session

EU Session Date: September 27, 2012 Time: 3:00 pm - 4:00 pm Central European Summer Time Register for European Session

Time does not fit your Schedule or Time Zone? We invite you to proceed with registration. Following the Webinar, all registrants are emailed a link to download the recorded Webinar Presentation to view at their convenience. To register or view more Aldec Events, please visit: http://www.aldec.com/events

Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs.

With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community.


Aldec market share is estimated at 38% of all mixed-language RTL Simulators sold to FPGA designers worldwide. (Excludes OEM simulators supplied directly from FPGA vendors). Aldec delivers high quality EDA solutions for government, military, aerospace, telecommunications, automotive and safety critical applications. Large companies including IBM, GE, Qualcomm, Rohde and Schwarz, Bosch, Texas Instruments, Applied Micro, Hewlett Packard, Toshiba, Intel, NEC, Mitsubishi, LG, Hitachi, NASA, Invensys, Westinghouse, Raytheon, Panasonic, Lockheed Martin, Samsung, as well as mid-size and small firms utilize Aldec EDA verification suites to boost product performance, cut design development cycles and reduce cost.