TSMC Open Innovation Platform® (OIP) Ecosystem Forum 2012

The TSMC Open Innovation Platform® (OIP) Ecosystem Forum brings TSMC’s design ecosystem member companies together to share with our customers real-case solutions for customers' design challenges and success stories of best practice in TSMC’s design ecosystem.

More than 90% of the attendees last year said "this forum helped them better understand the components of TSMC's Open Innovation Platform” and “they found it effective to hear directly from TSMC OIP member companies.”

Please introduce yourself if you see me. It would be a pleasure to meet you!

REGISTRATION




This year, the forum will feature a day-long conference starting with executive keynotes from TSMC and ARM in the morning plenary session to outline future design challenges and roadmaps, as well as discuss a recent collaboration announcement, 30 selected technical papers from TSMC's EDA, IP, Design Center Alliance and Value Chain Aggregator member companies, and an Ecosystem Pavilion featuring up to 80 member companies showcasing their products and services.

Agenda

San Jose Convention Center,
Tuesday , October 16th, 2012

Plenary Session
08:00	Registration Opens
09:00 – 09:10	Welcome Remarks		TSMC NA Executive
09:10 – 09:40	An Ecosystem for Innovation		TSMC Executive
09:40 – 10:10	TSMC Design Technology Update		TSMC Executive
10:10 – 10:40	ARM Feature Talk		Inviting Executive Level Speaker
10:40 – 11:00	Coffee Break

	EDA Track	IP Track	EDA/IP/Services Track
11:00 – 11:30	A Platform for the CoWoS Reference Flow Mentor Graphics	TSMC IP Kit V2.0 – Enhancing Soft IP Quality Standards Atrenta	SiP, 3D-IC & IPD Complement Flexible ASICs GUC
11:30 – 12:00	How to Manage Variability and Double Patterning at 20nm Cadence	1T-OTP – Non-Volatile Memory for Mobile and Other Low-Power Applications Sidense	Timing Sign-off and Technology Migration Using Functionalized Timing Reports IMEC
12:00 – 12:30	Finding and Fixing Double Patterning Errors in 20nm Design Mentor Graphics & TSMC	Implementing and Optimising Graphics IP in SoCs Imagination Technologies	Truly Differentiated Memory Subsystems on TSMC's Advanced Technology Nodes eSilicon
12:30 – 13:30	Lunch
13:30 – 14:00	Enabling 20nm Custom Design in Laker Springsoft	Advanced Silicon Design Methodology For Achieving 20nm Ready, Physical IP Synopsys	Publishing Innovation through IP Targeting TSMC Technology Design & Reuse
14:00 – 14:30	3D-IC Silicon Interposer IC Design Flow Using Cadence Encounter Digital Implementation (EDI) System Cadence	Comprehensive Embedded NVM Solution in Trusted Technology and Capacity Platform eMemory	TMI: A Unified Compact Model Development Platform for 28nm & Beyond Synopsys & TSMC
14:30 – 15:00	Verification of Power, Signal, and Reliability Integrity for 3D-IC/Silicon Interposer Designs ANSYS / Apache	Novel Low-Power Audio CODEC from 180nm to 28nm with Moore and More! Dolphin Integration	Design Methodology for Silicon-Accurate Jitter Analysis for 28nm Interface IP for 100GB Applications Berkeley Design Automation & Analog Bits
15:00 – 15:30	Coffee Break
15:30 – 16:00	TSMC Certification for Cadence 20nm RTL-to-GDSII Flow Cadence	Solving ESD, EOS and Latch-Up Requirements - For Analog Interfaces in Advanced CMOS - For Automotive Applications in TSMC's BCD Platforms SOFICS	Comprehensive Simulation and Modeling Solutions for TSMC's RF Platforms Agilent / EEsof
16:00 – 16:30	Double-Patterning Technology and Impact on 20nm Designs Synopsys	Enabling Design with Advanced Node Design IP for TSMC Cadence	Silicon-Accurate Mixed-Signal Fractional-N PLL IP Design Berkeley Design Automation & Silicon Creations
16:30 – 17:00	Improved Design for Reliability Using Calibre PERC Mentor Graphics	Kilopass Roadmap for Advanced TSMC Processes Kilopass	Chip-Partitioning Trends in Systems Using Ultra Deep-Submicron SoCs Cosmic Circuits
17:00 – 17:30	Automated Approach for Waiving Physical Verification Errors at IP Mentor Graphics & LSI	Using Latest-Generation DDR4, LPDDR3 and Wide-IO DRAM Devices with Chips in TSMC's Advanced 28nm and 20nm Processes Cadence	CMOS Silicon Millimeterwave Design Closure on Integrated Fullwave Electromagtic Simulation and Extraction Platform with a Real Silicon Design Case Lorentz & Stanford University
17:30 – 18:00	Networking and Reception

Legal Notice: TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.