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  • IC Layout Tools from Japan at DAC

    Last Monday I met with Nobuto Ono, VP Business development at Jedat (Japan EDA Technologies) while attending the DAC conference.

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    The company started in Tokyo and is Ex Seiko Instruments, in 2004.

    Main product - layout editor for IC (SX 9000). New system is ALpha SX in 2002. 2007 listed on JASDAQ market. Like Virtuoso tools, based on OA for AMS design.

    Major Customers - IDM, mask maker, LCD companies, over 200 companies mostly Japanese. A few Chinese LCD customers.

    Vision - automate custom IC design tools. Analog placement - Anchor Floorplan Package (better than Virtuoso). Cadence has Modgen, and Jedat is not presenting this in US market now.

    Support iPDK and member of IPL.

    IR Drop Analysis - PowerVolt, HayateDCC.

    Waveform viewer - SpiceChart

    Design Constraint Checker - HayatoDCC

    Floorplan Package - schematic capture and constraint management system for floorplanning. Based on OA database. Schematic driven layout. Read constraints from schematic, then auto place MOS devices. Analog block placement is automated. Can have a different layout hierarchy than schematic hierarchy. Result of automatic placement for a filter takes maybe 30 minutes.

    - no router yet, however use the Pulsic router as an engine. Can change the layout shape of any block from rectangular to rectilinear.

    IR Drop tool - Anchor PowerVolt
    - custom design IR drop tool, analog design and ER analysis.
    - both static and dynamic analysis at the transistor level.
    - demo of a Power MOS device. For transient analysis you supply the input stimulus. Viewer shows the mesh used for analysis, then colors of the rainbow used to show current density levels, animated as a function of time. Visualize current flow direction with arrows.
    - EM issues is determined by viewing the current density rules.
    - Also supports substrate currents.

    Final demo - LCD circuit, analyze ISS currents.

    Jedat has their own IC layout tools plus has partnered with other EDA vendors to offer IC sub-flows. The big challenge is name recognition against a crowded field of more well-known EDA suppliers.

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