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  • Physical IP Not From ARM or Synopsys

    ARM and Synopsys are well-known physical IP companies however at DAC today I met with a lesser-known company named DXCORR that has some unique offerings for cache, multi-port memory and standard cell kicker libraries. I met with:

    • R. Chandramouli, Director of Marketing
    • Dave Sinofski, VP Sales
    • Nirmalya Ghosh, CEO
    • Sagar Reddy, CTO



    Asynchronous design for 3D ICs-dxcorr-jpg


    What caught my attention about this start-up company is that Mark Templeton is acting President and also the founder of Artisan, which was sold to ARM.


    Ghosh - Ex ARM
    Reddy - Ex SIlicon Graphics
    Sinofsky - 30+ years
    Chandramouli - Ex ARM, Synopsys

    Asynchronous design for 3D ICs-screen-shot-2012-06-04-11-11-31-pm-jpg

    DXCORR was founded in 2005 and named by Sagar after an IC block that he designed. They have 32 engineers, mostly located in Bangalore, New Dehli and some folks in Sunnyvale, California.


    Physical IP has been created at the 40nm, 28nm and now 20nm nodes. This IP company is independent (unlike ARM, or EDA vendors), and only offers IP. GLOBALFOUNDRIES has fabbed their test chips at both 28nm and 40nm nodes.


    Pricing of their IP is similar to what Artisan did. Customers want different IP than what ARM is supplying, so if you need a faster cache than what Virage offers, come see DXCORR.


    IP from DXCorr is more custom fit per requirements as requested because they can generate instances across a wide range of options.

    Most of their EDA tools have been developed in house for physical layout generation while for verification they do use commercial tools like Calibre, as recommended by the foundries.


    Circuit simulation and timing of their IP is done with commercial tools like HPSICE and Spectre.


    Physical IP offered is: Custom cache and Multi-port Register File, where many versions are available. Binary and Ternary CAM plus standard cell kicker libraries are also offered.


    They don't use a Solido flow for variation aware design, and are using a statistical static timing analysis tool.


    All IP has a test chip and is silicon proven. A typical test chip contains about 70 instances of Register Files in various configurations of corner cases and typical cases. They use 32KB, 64KB and 16KB caches in their test chip because those are the most common sizes designed with today.

    Customer names cannot be shared at this time however they do include:

    • GLOBALFOUNDRIES
    • processor company
    • AMS IDM


    For reliability purposes each test chip has burn-in testing. During design they use both regular layout rules and recommended rules (95% or so) as defined by each foundry. Test chips do have a process monitor included.

    Success will be to continue to expand with existing customers and add more engagements. Keep growing the company organically. The plan is to have the three major foundries run test chips (it's a long cycle).

    The physical IP is delivered as GDS II, however it's not iPDK compatible. LEF, DEF, Verilog, CCS and common formats are used.


    The layout generators run on the Linux platform and DXCorr is currently working on 14nm node design concepts.




    Asynchronous design for 3D ICs-1000x120-gif