Apache has announced the latest version of RedHawk called RedHawk 3DX (the previous versions were SD for static-dynamic, EV for enhanced version, NX for next version and now 3DX for 3D extensions -- Apache didn't spend a lot on branding consultants!). This attacks some of the big issues connected with 3D, in particular the thermal problem (how much heat is there and what happens when you don't get it all out) and issues concerned with how you can analyze designs which are too large to analyze the old way.
There are 3 main changes:
- in keeping with its name, RedHawk 3DX is indeed ready for 3D and 2.5D ICs
- there is a gate-level engine in RedHawk now, enabling the RTL based analysis of PowerArtist to be pushed further
- there are changes in capacity and performance to keep up with Moore's law and take RedHawk down to 20nm designs
In 3D there are two big problems (apart from the sheer capacity issue of analyzing multiple die at once). The first is die-to-die power and die-to-die thermal coupling, and the other is modeling TSVs and interposers (which obviously you don't have unless you are doing 3D).
With a multi-pane GUI you can now look at the different die and the interposer and see the thermal effects. TSVs are obviously an electrical connection between adjacent die but they are (often) made of copper and are a good thermal connection too. This can be good (the next die is a sort of heatsink) or bad (DRAM doesn't like to get hot). You can look at voltage drop issues to make sure you don't have power supply integrity problems, and also at current and thermal.
The second big change is that the RTL analysis approach of PowerArtist is pushed into RedHawk. PowerArtist does RTL analysis and prunes the simulation vectors down to perhaps a few hundred critical ones where power transitions occur or where power is very high (for example, inrush current when a powered down block is re-activated). These few vectors need more detailed analysis down at the level RedHawk operates. There is also a vectorless mode. You can see in the pictures below how well the RTL level analysis matches the gate-level analysis, both in the numbers which differ by a few percent and just visually looking at the voltage drop color maps.
Of course on a large chip you want the capability to analyze different blocks at different levels, some at gate, some at RTL, some vectorless, and you can do that.
The third aspect of the new generation of RedHawk is keeping up with design size. There is a new sub-20nm electromigration signoff engine which is current direction aware, metal topology aware and temperature aware (all things that affect EM).
Plus, adding an extraction reuse view enables a reduced model of part of the power delivery network. This enables up to (actually occasionally more) 50% reduction in the simulation node-count without reducing accuracy. This enables full-chip simulation including the package impact, with blocks of interest analyzed in detail and other blocks reduced using the ERV approach.