But memories are different. They have fewer layers of metal and end up with long narrow areas between the memory arrays and around the outside. Memories are also early into new processes and the first that have to deal with more restricted design rules. As a result, there is a need for routing this sort of area with long jogless nets, just like in the old days of 3-layer metal ASICs.
Normal digital place and route, or a shape-based router, does not give the right results, producing too many jogs, too many vias and is not controllable enough by the designer. But a straightforward implementation of a 1980s channel router isn't adequate either. The connection points are inside the blocks, care needs to be taken feeding signals through the blocks. What is required is a smart way to create the pins that is aware of just how the channel router is going to behave. Otherwise it is too easy to create designs where one pin blocks another route (remember, we are avoiding jogs and vias). The router needs to drive the pin placement.
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