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  • Need and Opportunity for Higher Analog Automation

    Article: Mentor Graphics 1 : Carl Icahn 0!-analog1.jpgConsidering the days when designs were all custom done by hand; GDSII (which still survives and is de-facto standard, invented by Calma, now Cadence) being the format to represent the design and SPICE along with its models being the tool for verification, it would not be inappropriate to say that the very basis of a design is Analog from historical as well as design leaf cell perspective. Although automation for placement, routing and verification started at that time, the real push in increasing the design size, complexity, speed and TAT came after the arrival of HDLs (Verilog, VHDL) which opened the channel of specifying the design in easily readable textual format. Combined with HDLs, standardization of leaf cells and set of automated tools to verify and transform the design at multiple stages from text up to GDSII format opened the era of Digital design methodology. This along with further innovations in semiconductor technology and design automation tools led to large design (with millions of transistors) manufacturing into ICs at deep-sub-micron level of the order of 90nm and below.

    In the whole journey, while there has been tremendous advancement in Digital design automation, Analog design automation has been incremental and mostly remained in silos. With the increase in design size and significant part of it being Analog there was a need for Analog Digital mixed-signal (AMS) design optimization and verification. In this article my emphasis is on Analog rather than Digital because as far as design is concerned, it is done separately for Analog and Digital parts and then assembled together, although several methodologies are being developed to accommodate each other on a single chip. Let’s see how the automation has progressed in Analog space so far –

    Cell/Block Design – This is the very initial phase to develop the base level design cells or blocks of design. Cadence pioneered the Pcell methodology which is SKILL language based and designer has to program the cell as per his/her need. This methodology became very popular in the design community and several variants of Pcell with varying characteristics emerged such as Mcell by SpringSoft, Flexcell by Magma, Pycell by Ciranova and so on.

    Function/Device Generators – These are like macro level cells used as design components such as differential pairs, current mirrors, resistors, capacitors, guard bands etc. and are very specialized for different types of circuits. EDA players like Cadence and Mentor do have these, but recent offering of HiPer DevGen by Tanner seems impressive.

    Article: Mentor Graphics 1 : Carl Icahn 0!-analog2.jpg
    A sample current mirror

    Schematic Driven Layout – This is another level of automation where Analog design is done at schematic level, verified and then layout is generated from schematic automatically. However, iterations are involved, both at schematic and layout (after parasitic extraction and re-verification) level for optimizing and meeting the requirements. This level of automation is available with all three Cadence, Mentor and Synopsys. Magma (now Synopsys) has introduced Analog Design Accelerator (ADX) which uses models (using equations) for designs provided by designers along with process and design constraints and optimizes the schematic automatically.

    Verification – Circuit simulation is the area where most of the automation work has been done in Analog and AMS space. When design sizes increased with significant Analog part into it, there was need for mixed-signal simulation as well as improvement in speed of simulation in order to verify the overall design. Cadence took lead in offering MMSIM which catered to SPICE with Digital, spectre and spectre RF accepting Verilog A and spectre MDL. Accelerated Parallel Simulator reduced simulation run time to large extent and Ultrasim handled hierarchy. Improved circuit simulators along with HDL simulators (Verilog, VHDL, SystemVerilog, SystemC) are being provided by all major players like Cadence, Synopsys and Mentor.

    Article: Mentor Graphics 1 : Carl Icahn 0!-analog3.jpg

    It is clear that Analog automation has remained reactive until needed. This level of automation in Analog has probably worked till 90nm where Guard band has been used to shield the Analog part from neighbouring physical effects. In today’s world at 45nm and below, systematic variation effects such as Well Proximity Effect (WPE), Shallow Trench Isolation (STI) stress, Poly Spacing Effect (PSE) and Length of Diffusion (LOD) have become prominent. These fall in Analog domain and depend on device parameters as well as their relative placement in the chip. Their detrimental effects can alter transistor characteristics such as threshold voltage and gain altogether. While we are moving down to 20nm and below, there is acute need to address these issues by automatically detecting and preventing them early in the design cycle. A few companies are working towards solving these issues, e.g. Solido Variation Designer from Solido Design Automation can detect WPE and recommend specific modifications in a transistor.

    So far I talked about the need of automation in the Analog space. Now I would like to talk about the opportunity in this space. As we see Analog design, it is majorly based on constraints. With the use of constraints as the guiding parameters, Analog design can be automated to large extent. EDA vendors like Cadence and others are developing constraint driven flows, but those constraints are internal to their tools. The industry needs a common open standard format for Analog constraints (including symmetry, matching, shielding, placement, floorplanning, routing, clocking, timing, and electrical and so on) which we do not have so far. Open Access database has defined constraint, but they are mostly at foundry level. We need design level constraints as well which should be in standard open format. These should be able to be parsed from textual input as well as graphical and then applied as constraints for transistors and Analog components during their physical placement and routing. The first and foremost advantage of this will be interoperability, thereby leading to designer productivity. In my view, this should also unleash opportunity for automation in the Analog space. Of course lot of pre-work has to be done, specifically for electrical constraints, to infer from foundry models and translate them into constraints to be applied on the design. The good news is that IPL Alliance has initiated to define the constraint format with the introduction of its first version in 48th DAC. It is yet to be available for general use. Definitely, with wider use of the standard, lot of enhancements in the format itself as well as Analog design automation is expected to take place. But before that happens, major semiconductor community including foundries, fabless design companies and EDA vendors need to adopt the common standard for Analog constraints and also contribute to its development into a rich proven set of constraints.

    By Pawan Kumar Fangaria
    EDA/Semiconductor professional and Business consultant
    Email: Pawan_fangaria@yahoo.com

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